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Structure and method for simultaneously determining an overlay accuracy and pattern placement error

一种准确度、结构组件的技术，应用在堆栈材料层领域，能够解决限制切割线可用空间、高生产力、低制造成本等问题

Inactive Publication Date: 2008-10-01
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] Due to the increasing demand for higher productivity and lower manufacturing costs, it is also possible to reduce the size of the cutting line, thereby significantly limiting the space available for any measurement area within the cutting line

Method used

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  • Structure and method for simultaneously determining an overlay accuracy and pattern placement error
  • Structure and method for simultaneously determining an overlay accuracy and pattern placement error
  • Structure and method for simultaneously determining an overlay accuracy and pattern placement error

Examples

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Embodiment Construction

[0028] Hereinafter, embodiments of the present invention will be described. In the interest of clarity of illustration, not all features of an actual implementation are described in this specification. However, we should understand that when developing any such real implementation, many implementation-related decisions must be made in order to achieve the developer's specific goals, such as meeting system-related and business-related constraints, while These constraints will vary from implementation to implementation. Moreover, it should be understood that such a development effort might be complex and time consuming, but would nonetheless be a routine undertaking for those with ordinary knowledge of the art having the benefit of the present disclosure .

[0029] The invention will now be described with reference to the accompanying drawings. Various structures, systems and devices are shown schematically in the drawings for purposes of illustration only, in order not to ob...

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PUM

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Abstract

The present invention provides a technique for obtaining overlay error and pattern placement error information from a single measurement structure (200) This is accomplished by forming periodic sub-structures (210, 220, 240, 250) in at least two different device layers in a single measurement structure (221,241), wherein at least one segmented (200) and one non-segmented (211,251) portion is provided in the two different device layers.

Description

technical field [0001] The present invention relates to the field of manufacturing integrated circuits, and more particularly to a method for estimating overlay accuracy and pattern placement error ( Pattern Placement Error (referred to as PPE) method and structure. Background technique [0002] The fabrication of microstructures, such as integrated circuits, requires the formation of precise and precise substrates in material layers of suitable substrates such as silicon substrates, silicon on insulator (SOI) substrates, or other suitable carrier materials. Some tiny areas of controlled size. Create patterns in layers of material by performing processes such as lithography, etching, ion implantation, deposition, and oxidation processes to create these tiny regions of precisely controlled dimensions, usually at least during some stage of the patterning process A mask layer (mask layer) can be formed on the material layer to be processed to define these tiny areas. In gene...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20
CPCG03F7/70683G03F7/70633H01L2924/0002H01L23/544H01L2924/00G03F7/70625
Inventor B·舒尔茨
Owner GLOBALFOUNDRIES INC
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