Method and system for calculating delayed statistics variation caused by coupling event between two adjacent networks in integrated circuit design

A technology of integrated circuits and adjacent networks, applied in the field of statistical computing, can solve problems such as low efficiency, pessimism, and variation

Inactive Publication Date: 2010-09-29
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The second disadvantage is that using worst-case analysis is unnecessarily pessimistic
[0012] A third disadvantage is that, for a comprehensive analysis, multiple combinations of process variations must be analyzed
However, this exhaustive analysis is inefficient

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  • Method and system for calculating delayed statistics variation caused by coupling event between two adjacent networks in integrated circuit design
  • Method and system for calculating delayed statistics variation caused by coupling event between two adjacent networks in integrated circuit design
  • Method and system for calculating delayed statistics variation caused by coupling event between two adjacent networks in integrated circuit design

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Embodiment Construction

[0024] The invention and its various features and advantages are elucidated with reference to the non-limiting embodiments shown in the drawings and described in detail in the following description. It should be noted that the features shown in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as not to unnecessarily obscure a detailed understanding of the present invention.

[0025] image 3 is a flowchart showing one embodiment of a static timing analysis method 300 for an integrated circuit design according to the present invention. Method 300 can be implemented to analyze combinational integrated circuit designs and sequential integrated circuit designs. As will be described in detail below, the method 300 accurately and efficiently handles process variation and coupling events in the static timing analysis process, while also considering complex dependencies introduced by the process variation...

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Abstract

The invention discloses a method and a system for calculating the delayed statistical change generated due to a coupling event between two adjacent networks in an integrated circuit design. In one embodiment, the invention relates to a method and a device which are used for implementing a static timing analysis when the coupling event and the process variation are existed. The method for calculating the relayed and the converted statistical change generated due to the coupling event between the two adjacent networks in the integrated circuit design includes an execution of a statistical timing analysis of the integrated circuit design and a calculation of statistical overlapping windows between the networks, wherein, the statistical timing window statistically represents a time segment inwhich signals on the adjacent networks can be switched simultaneously. The method also includes that a delayed statistical change generated due to the coupling event is calculated according to the statistical overlapping window.

Description

technical field [0001] The present invention generally relates to the field of design automation, and more specifically, the present invention relates to the statistical calculation of the impact of coupled noise of integrated circuits on static timing. Background technique [0002] The main goal of static timing analysis (STA) is to verify the timing correctness of integrated circuits. However, traditional static timing analysis does not consider the impact of coupled noise on timing. [0003] Coupling capacitance exists when two adjacent wires in an integrated circuit are very close to each other. Depending on how the signal rises or falls on these wires, capacitive coupling can cause variations in the delay and slew (number of transitions) of the gates and wires. For example, if the signals on two adjacent wires are switching in the same direction (i.e., rising or falling at the same time), the coupling capacitance between those two wires causes the voltages at their tw...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 尚德莫里·维斯威斯瓦雷所罗施·阿巴斯波格里高利·M.·谢菲尔
Owner IBM CORP
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