A device and method for FPGA simulation

Abstract

The invention discloses an FPGA simulation device and a method thereof; the device comprises a configuration module configuring and conserving message parameters determined according to random design requirements, an incentive message generating module in inlet connection with the configuration module and used for generating and sending incentive messages to a memory module, a bus interface module connected with an FPGA logical module to be tested and providing interfaces and a bus required by the testing of the FPGA logical module, a message comparison module in inlet connection with the memory module and used for comparing incentive messages with the response messages input by the FPGA logical module to be tested and returning the comparative result to the memory module for conservation, together with an RAM stuffer in inlet connection with the configuration module and used for filling contents to the random access memory RAM. The FPGA simulation device and the method thereof greatly reduce the processing time for verifying the functions of a plurality of RAM interfaces of the FPGA logical module to be tested and enormously increase the efficiency of the FPGA logical simulation verification.

Description

technical field [0001] The present invention relates to the field of data communication, in particular to FPGA simulation technology, in particular to a device and method for FPGA simulation. Background technique [0002] With the development of data communication technology, especially the emergence of high-bandwidth and high-speed data communication technology, in the design of data communication chips, large-scale, high-speed, high-complexity data communication chip designs emerge in an endless stream, especially those based on FPGA. In large-scale logic design, the completed logic functions are numerous and complex. Usually, in order to ensure the reliability of the FPGA logic design in practical applications, the designed FPGA logic needs to be simulated and verified before it is put into use. In order to improve the efficiency of simulation, there are some devices specially used to verify and simulate the FPGA logic. . [0003] Existing verification simulation device...

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Problems solved by technology

[0013] The purpose of the present invention is to propose a method and device for FPGA simulation, which is mainly used to solve the problems of long time and low efficiency for FPGA logic simulation verification at present

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