Method and circuit for transferring data across multiple clock domains

Abstract

The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream and a sampling module sequentially samples and outputs each signal in the first group signals and the second group signals by the N sampling pulses with a sequence.

Description

technical field [0001] The present invention relates to a method and device for transmitting data streams, in particular to a method and device for transmitting data streams in multiple time domains. Background technique [0002] Generally, circuits controlled by transmission data streams passing through multiple time domains are the most common phenomenon in circuit systems. For example, Figure 1A shows a schematic circuit diagram of existing transmission data passing through three time domains. The data stream in time domain D14 The data_010 is first sampled by the sampling frequency clk117 to become the data stream data_111 in the time domain D+115, and the subsequent data stream data_212 is sampled by the sampling frequency clk218 to become the data stream data_313 in the time domain D+216 and so on. [0003] However, even if the above-mentioned sampling frequencies have the same frequency, jitter or frequency distortion (skew) will occur at the edges of the sampling wav...

AI Technical Summary

Problems solved by technology

The traditional downsampling ambiguity solution is to use 3 different frequencies sel_0, sel_1 and sel_2 to sample the data data0, data1 and data2 in the K-frame respectively. However, due to jitter and frequency distortion, the frequency sel_0 is sampled Sampling blur also occurs near the edge of the sampling frequency clk1

Images