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Low density parity check (ldpc) decoder

A low-density parity and check code technology, applied in the field of data receivers

Inactive Publication Date: 2007-09-05
THOMSON LICENSING SA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Unfortunately, there is no consistent design methodology for efficiently implementing partially parallel LDPC decoders

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  • Low density parity check (ldpc) decoder
  • Low density parity check (ldpc) decoder

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Embodiment Construction

[0026] Except for the inventive concept, the elements shown in the figures are well known and will not be described in detail. For example, satellite transponders, downlink signals, symbol constellations, carrier recovery, interpolation, phase-locked loops (PLLs), radio frequency (rf) front-ends, or receiver sections such as low-noise block down-conversion Formatting and encoding methods (such as Moving Picture Experts Group (MPEG)-2 system standard (ISO / IEC 13818-1), LDPC encoding, etc.) used to generate the transport bit stream, and decoding methods such as log likelihood ratio , Soft-Input Soft-Output (SISO) decoder, and Viterbi (Viterbi) decoder are well known and will not be described here. Additionally, conventional programming techniques can be utilized to implement the inventive concepts and thus are not described here. Also, the reader is assumed to be familiar with satellite based systems (such as DVB-S2) and the aforementioned ETSI draft EN 302307, v.1.1.1, (June 2...

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Abstract

A satellite receiver comprises a front-end, demodulator and an LDPC decoder. The front-end receives a DVB-S2 LDPC coded signal and provides a down-converted signal to the demodulator. The latter demodulates the down-converted signal and provides a demodulated signal to the LDPC decoder. The LDPC decoder has a partially parallel architecture and partitions the bit node messages into N / 360 groups and the check node messages into q groups, where q = M / 360. Each group is processed by 360 bit node processors or 360 check node processors, respectively. Illustratively, the LDPC decoder includes a memory that is partitioned such that messages associated with bit node groups are consecutively addressed. Alternatively, the LDPC decoder includes a memory that is partitioned such that messages associated with check node groups are consecutively addressed.

Description

technical field [0001] The present invention relates generally to communication systems, and more particularly to a receiver that processes Low Density Parity Check (LDPC) encoded data. Background technique [0002] In recent years, LDPC codes have gained popularity due to their near-Shannon limit error correction capability. For example, the second-generation digital video broadcasting standard (DVB-S2) adopted LDPC codes as the main error-correcting codes to replace the convolutional codes used in the first-generation DVB standards (see, for example, the European Telecommunications Standards Institute (ETSI) draft EN 302307, v.1.1.1, (June 2004)). [0003] In general, (N,K)LDPC codes are parity-check codes, where K is the number of bits to be encoded, N is the size (length) of the resulting encoded block, and (N-K) is the additional error correction bits added by the code. The (N, K) LDPC code can be expressed in matrix form as the following matrix equation Hx T =0 T T...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11H03M13/00
CPCH03M13/616H03M13/1105H03M13/1111H03M13/1137H03M13/1165H03M13/1168H03M13/1185H03M13/11
Inventor 高文库马尔·拉马斯瓦米约翰·赛迪·斯图尔特
Owner THOMSON LICENSING SA
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