Variegated BIST test approach

Abstract

The invention relates to a method for chip testing and discloses a diversified test method for BIST, which comprises the following steps: test the NVM through the logic Interface unit; convert the test image to the instruction set in the code form and store in the NVM area; the CPU enabled by the external instructions reads the instruction set in the NVM area and energizes the circuit in the chipaccording to the instruction set; after receiving the response, return the PWL or code on the inport or output; erase the code in the NVM, repeat the above steps and then conduct operation of the nexttest image. The diversified test method for BIST provided in the invention can greatly save the chip area and test channel, increase the concurrent-testing capacity and reduce the dependence to the test hardware.

Description

technical field [0001] The invention relates to a chip testing method, in particular to a BIST (Built In Self Test, built-in self-test) testing method. Background technique [0002] During the chip test, the tester is used to apply excitation to the chip from the outside, and then the response is compared with the expectation to judge whether the chip is a good product. [0003] More complex chips need more pins, lead out the channels required for testing and connect them with the testing channels, one-to-one correspondence, receive the excitation of the tester, and return the signal to the tester for judgment, but this method The chip area is too large and the cost is too high. [0004] In order to save the chip area, some designs will reduce the PAD of the chip and reduce the test channels. In order to achieve the same error coverage, the depth of the test pattern will inevitably be deepened. However, existing testers or some test software may not be able to meet these r...

AI Technical Summary

Problems solved by technology

[0007] In order to solve the problem of too large area and increase the number of simultaneous measurements, some SOC designs add serial port circuits to pass all excitation signals through very few PADs (pins) such as figure 1 There are only PAD1 and PAD2 in the middle, so to take into account all the test error coverage, the depth of the excitation signal is bound to increase a lot, the test time increases, and the ability of the hardware graphics of the tester is challenged

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