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Semiconductor memory device with reduced power consumption for refresh operation

a memory device and memory technology, applied in the field of semiconductor memory devices, can solve problems such as unnecessary current consumption, and achieve the effect of avoiding needless current consumption

Inactive Publication Date: 2006-01-31
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0017]It is a general object of the present invention to suppress current consumption in a semiconductor memory device having the configuration in which shift registers select a word line for refresh operation.
[0018]It is another and more specific object of the present invention to reduce current consumption consumed by a word decoder set not subjected to a refresh operation in a semiconductor memory device having the configuration in which shift registers select a word line for a refresh operation with respect to a plurality of word decoder sets.
[0021]In the semiconductor memory device as described above, the shift control signal is supplied only to a selected one of the word decoder columns, thereby making it possible to avoid needless current consumption in the unselected word decoder columns (word decoder sets).

Problems solved by technology

This results in unnecessary current consumption.

Method used

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  • Semiconductor memory device with reduced power consumption for refresh operation
  • Semiconductor memory device with reduced power consumption for refresh operation
  • Semiconductor memory device with reduced power consumption for refresh operation

Examples

Experimental program
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first embodiment

[0044]FIG. 3 is a diagram showing the construction of a shift register controlling circuit according to the present invention.

[0045]The shift register controlling circuit of FIG. 3 includes a shift register (S / R) 40, a right / left-array selecting circuit 41, a shift control signal generating circuit 42, and a shift control signal generating circuit 43. The shift control signal generating circuits 42 and 43 generate shift control signals clk—l and clk—r for provision to the word decoder sets 14-1 and 14-2, respectively. The word decoder sets 14-1 and 14-2 are as illustrated in FIG. 1 and FIG. 2. The shift control signal clk—l is supplied as the shift control signal cntl shown in FIG. 2 to the word decoder set 14-1 corresponding to the left-side cell array unit 13-1. The shift control signal clk—r is supplied as the shift control signal cntl shown in FIG. 2 to the word decoder set 14-2 corresponding to the right-side cell array unit 13-2.

[0046]In FIG. 3, the shift register 40 is provid...

second embodiment

[0072]FIG. 11 is a drawing showing the construction of the shift register controlling circuit according to the present invention. In FIG. 11, the same elements as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

[0073]In the construction shown in FIG. 11, the shift register 40 of the construction shown in FIG. 3 is replaced by a counter-&-decoder circuit 40A. The counter-&-decoder circuit 40A includes a counter for counting up (or counting down) in synchronization with the clock signal clk, and further includes a decoder for decoding the count of the counter. With this provision, it is possible to provide the function equivalent to that provided by the shift register 40. In should be noted that as decoder outputs, only the counter decoded values corresponding to the signals r1, r2, 11, and 12 of FIG. 4 may be output. This makes it possible to implement a decoder by use of a small-scale circuit.

third embodiment

[0074]FIG. 12 is a drawing showing the construction of the shift register controlling circuit according to the present invention. In FIG. 12, the same elements as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

[0075]In the construction shown in FIG. 12, a check as to which one of the right and left arrays is in the selected state is made by utilizing the outputs of the word line selecting shift registers 82 arranged in the word decoder sets 14-1 and 14-2, rather than using the shift register 40 as in the first embodiment or the counter-&-decoder circuit 40A as in the second embodiment. Specifically, the output of the word line selecting shift register 82 situated at the turning-back point from the left-hand side to the right-hand side is denoted as r1, and the output of the word line selecting shift register 82 situated at the turning-back point from the right-hand side to the left-hand side is denoted as 11. Further, the output of th...

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Abstract

A semiconductor memory device includes a plurality of word decoders arranged in a plurality of columns, a plurality of word line selecting shift registers corresponding to the respective word decoders to indicate a word line subjected to refresh operation, and a shift control signal generating circuit operable to supply a shift control signal indicative of timing of shift operations to the plurality of word line selecting shift registers, wherein the said shift control signal generating circuit is configured to supply the shift control signal only to a column currently subjected to refresh operation among the plurality of columns.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This is a continuation of International Application No. PCT / JP2003 / 005203, filed on Apr. 23, 2003, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which performs refresh operations for retaining stored data.[0004]2. Description of the Related Art[0005]There is a strong demand for low power consumption with respect to semiconductor devices for use in portable equipment.[0006]In DRAMs that store data in memory capacitors, refresh operations are constantly performed to retain information stored in the cells by successively activating word selecting lines to read cell data, amplifying the data potentials by use of sense amplifiers, and writing the amplified data back to the cells. Such refresh operations are performed even during a st...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C7/00G11C7/10G11C8/08G11C11/406G11C11/4063G11C11/408
CPCG11C7/1018G11C8/08G11C11/4087G11C11/40618G11C11/406
Inventor TAKITA, MASATOKAWABATA, KUNINORI
Owner SOCIONEXT INC
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