Method to improve transistor tox using si recessing with no additional masking steps

Abstract

A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source / drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source / drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source / drain regions. Source / drain regions are implanted or grown by a selective epitaxial growth.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This Application is a continuation of U.S. application Ser. No. 11 / 868,787 filed on Oct. 8, 2007, entitled A Method To Improve Transistor Tox Using Si Recessing With No Additional Masking Steps, commonly assigned with the present invention and incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to various methods for the manufacture of transistor devices to improve poly depletion and oxide thickness.BACKGROUND OF THE INVENTION[0003]Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and...

AI Technical Summary

Benefits of technology

[0010]In one example, the silicon germanium material is doped with boron in-situ for the formation of p-type extension regions. In another example, an extension region implant is performed into the silicon germanium material after the selective epi deposition, followed by the formation of sidewall spacers and source / drain implants. Having the boron doped silicon germanium material (either doped in-situ or via implantation) close to the gate as opposed to laterally spaced away (e.g., at the source / drain locations) advantageously allows less germanium to be employed in the recesses for a given desired stress, thereby reducing threading dislocation defects.

[0012]In one example, the silicon germanium material is doped with boron in-situ for the formation of p-type extension regions. In another example, an extension region implant is performed into the silicon germanium material after the selective epi deposition, followed by the formation of sidewall spacers and source / drain implants. Having the boron doped silicon germanium material (either doped in-situ or via implantation) close to the gate as opposed to laterally spaced away (e.g., at the source / drain locations) advantageously allows less germanium to be employed in the recesses for a given desired stress, thereby reducing threading dislocation defects.

Problems solved by technology

However, too much doping in the source / drain regions can lead to overrun of the extension regions, and lead undesirably to punchthrough and / or leakage.

The excellent abruptness of SPER junction results from a poor activation level in the crystalline Si below the amorphous region.

Despite the excellent vertical junction profile, several integration issues rise from the lateral amorphisation and from the End of Range (EOR) defects.

Unless optimized this leads to poor doping active concentration under the gate that significantly increases the overlap resistance.

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