High order sigmatriangle noise shaping interpolator for direct digital frequency synthesis

Abstract

The invention relates to a high-order sigma delta noise rectification interpolator used in direct digital frequency synthesizer. The invention comprises a rectification accumulator (22), a delay circuit (23) and a phase accumulator (20). The external N bit frequency is input into the phase accumulator (20) whose output is connected to the rectification accumulator (22); the output of rectification accumulator (22) is used as the high p bits of the phase of sine or cosine and as the lower N-p bits of cut section, to connect the delay circuit (23) to process the transmission function as 1-(1-Z-1)n, to be output to the rectification accumulator (22); the output of rectified phase is connected to the sine or cosine look-up list (30) whose output via the digital / analogue converter (40) and the low-pass filter (50) is transformed to the sine or cosine wave with lower noise.

Description

technical field [0001] The invention relates to the technical field of digital frequency synthesis, in particular to a ΣΔ noise shaping interpolator for improving the dynamic characteristics of a direct digital frequency synthesizer (DDFS). Background technique [0002] Direct digital frequency synthesizer (DDFS) is an important low-cost high-resolution frequency synthesis method. Unlike PLL-based synthesizers, DDFS is fully compatible with digital CMOS processes and is often embedded in baseband ASIC transceivers. Although DDFS has been around for many years, it can only be applied to narrow-band frequency synthesis due to the performance limitations of digital logic circuits and digital-to-analog converters. Recently, with the improvement of digital logic circuit and digital-to-analog converter technology, DDFS has become the mainstream of broadband frequency synthesis. like figure 1 As shown, a conventional DDFS includes a phase accumulator 20 that generates a phase va...

AI Technical Summary

Problems solved by technology

The most straightforward solution is to increase the length of the phase word, but this will result in a drastic increase in synthesizer hardware

And along with the increase of phase words, the number of bits of phase accumulator 20 also increases thereupon, will affect the speed of phase accumulator 20 accumulation like this

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