Logic verification system and method

Abstract

This invention discloses a logic verification system including an excitation generating module, a tested logic module, a result analysis module, a test interface module, a storage module a bus functional module realized by hardware. A method for logic verification includes: generating exciting data necessary for test, writing the exciting data into the needed verified logic chips via different interfaces when carrying out emulation and hardware system verification verifying if the logic is correct based on the output result of the logic chips.

Description

technical field [0001] The invention relates to the technical field of electronic testing, in particular to a logic verification system and method. Background technique [0002] Programmable Logic Device (PLD) has experienced several development stages of PAL (Proprietary Array Logic), GAL (General Array Logic), CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array). The use of PLD has many advantages such as flexible design, convenient debugging, high system reliability, etc., and is conducive to the protection of hardware design, preventing others from analyzing and imitating the circuit, making it the first choice for scientific research experiments, prototype trial production and small batch products. Therefore, programmable logic devices have been widely used in data communication systems. In the development and design of systems and equipment using programmable logic devices, it is necessary to verify the correctness of the implemented logic...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a logic verification system and method, to overcome the shortcomings of the prior art that resources cannot be reused and shared in simulation verification and hardware system verification, and improve the efficiency of logic verification

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