Data processing system capable of processing program utilizing virtual memory

Abstract

An access request for a data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk. When a specific set of data is needed, a processing unit generates a virtual memory access request to be received by the storage controller. The storage controller then fetches the data for the requesting processor. The virtual memory access request includes a group of hint bits regarding data prefetch associated with the fetched data.

Description

technical field [0001] The present invention relates generally to data processing systems, and more particularly to data processing systems having memory hierarchies. More particularly, the present invention relates to data processing systems capable of managing virtual memory processing schemes without the assistance of an operating system. Background technique [0002] Prior art memory hierarchies typically include one or more levels of cache memory, a system memory (also known as real memory), and hard disks (also known as physical memory) connected to the processor complex via input / output channel converters. ). When there are multiple levels of cache memory, the first level cache memory (commonly referred to as Level 1 "L1" cache) has the fastest access (access) time and highest cost per bit. The remaining levels of cache memory, such as Level 2 "L2" cache, Level 3 "L3" cache, etc., have relatively slow access times, but also relatively low cost per bit. Typically ea...

AI Technical Summary

Problems solved by technology

However, there are several problems with virtual memory managed by the operating system

For example, VMMs generally ignore hardware structures, so replacement policies specified by VMMs generally must not be effective

Furthermore, the VMM code is complex and expensive to maintain across multiple hardware platforms or even a single hardware platform with many different possible memory configurations

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