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Treating method and system for local defect internal memory

A processing method and a processing system technology, which are applied in the processing and system field of local defect memory, and can solve the problem that CPU1 cannot recognize the instruction part, etc.

Inactive Publication Date: 2004-09-22
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Generally, CPU1 cannot identify which is the instruction part, which is the data part or the stack part through the standard fetching and decoding actions.

Method used

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  • Treating method and system for local defect internal memory
  • Treating method and system for local defect internal memory
  • Treating method and system for local defect internal memory

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0071] Fig. 3 shows a configuration diagram of the local defect memory processing system of the first embodiment. In FIG. 3 , the memory 3 includes at least one defective storage unit. In the following descriptions, unless otherwise specified, a single defective storage unit or a group of adjacent defective storage units is used as a preset condition. The CPU 1 is preparing to load the original program code 20 into the memory 3 through the data / address bus 10 , and the storage units to be loaded by the original program code 20 include the defective storage units mentioned above. Therefore, the loader (loader) executed in CPU1 must perform some pre-processing actions to ensure that the loaded original program code 20 will not occupy the defective storage unit, and the original program code 20 itself can still be normal. implement. In this embodiment, CPU1 and memory 3 can coexist in the same integrated circuit, such as the application of a single chip system (system on a chip)...

no. 2 example

[0089] Although the processing method of a certain program has been disclosed in the first embodiment, which can solve the problem of partially defective memory, there are still some programs that can be changed. For example, this embodiment is produced by changing the scanning processing method of the original program code and the order of loading the memory from the first embodiment.

[0090] FIG. 9 shows a flow chart of the local defect memory processing method of the second embodiment. As shown in Figure 9, on the one hand, CPU1 determines the physical location of the defective storage unit (S20) and determines the corresponding defect address (S21) of the defective storage unit in the original program code 20; 20 performs scanning (S22). The defect address of the defective storage unit can be determined by step S20 and step S21, and the divisible break point in the original program code 20 can be determined by step S22. This synchronization processing can be applied to ...

no. 3 example

[0094] The first and second embodiments are applicable to the situation that the original program code has not been loaded into the internal memory. At this time, the CPU (microprocessor) can perform pre-processing before the original program code is loaded into the internal memory, so as to adjust the program code to Avoid defective memory cells. However, the situation to be dealt with in this embodiment is the phenomenon that the original program code has been successfully loaded into the memory, but some storage units show weakened functions after a period of time. These degraded memory cells can be read normally at present, but after a certain period of time, the logic value read from them will become increasingly illegible. At this time, the original program code content in the memory must be adjusted to avoid these defective storage units with weakened functions.

[0095] Fig. 10 shows a configuration diagram of a local defect memory processing system of the third embodim...

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Abstract

During treatment of local defect memory, original program codes are scanned and first breakpoint and second breakpoint are set in the addresses corresponding to the front and back of the defect memory units separately. The program code section in the defect area is shifted to between the first address and the second address in other normal area. The shifted program code section is connected to the un-shifted parts of the original program codes and the reference addresses are regulated. The modified program is then loaded into the memory. The said method and system can keep away from the defect memory units without affecting the execution of the original program.

Description

technical field [0001] The present invention relates to a processing method and system for locally defective memory, and in particular to a processing method and system, which can adjust the program code that has not been loaded into the memory or already exists in the memory, so that the program code is still Can be loaded into memory with partially defective memory cells and executed. Background technique [0002] In the past, if there were any defective memory cells in the memory IC, such memory IC would not be sold on the market. In order to reduce the scrapping of the entire IC due to a single or a small number of defects, there are currently many technologies that can make a partially defective memory IC operate like a completely normal memory IC. [0003] For example, US Patent No. 4939694 discloses a memory system capable of self-testing and self-repairing. The memory system can be self-tested in the field to locate defective memory cells. Once any defective memor...

Claims

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Application Information

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IPC IPC(8): G06F11/10G11C7/00G11C29/00
Inventor 林锡聪
Owner WINBOND ELECTRONICS CORP
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