Chip packaging method, chip packaging body and electronic device

Abstract

The invention discloses a chip packaging method, a chip packaging body and an electronic device, and the method comprises the steps: providing a bearing plate which is provided with a first surface and a second surface which are opposite to each other; forming a first through hole and a second through hole in the bearing plate, and electroplating a metal layer to form a first bonding pad and a second bonding pad on the bearing plate; wherein the first bonding pad comprises a first connecting column, a first welding surface and a second welding surface which are used for filling the first through hole, the second bonding pad comprises a second connecting column, a third welding surface and a fourth welding surface which are used for filling the second through hole, and the first welding surface and the third welding surface are attached to the first surface of the bearing plate; the second welding surface and the fourth welding surface are attached to the second surface of the bearing plate; arranging a chip on the first bonding pad, and carrying out plastic package on the chip to form a first plastic package layer; and forming a metallization layer on one side, far away from the bearing plate, of the first plastic packaging layer so as to electrically connect the back surface of the chip with the second bonding pad. In this way, the welding reliability of products can be improved.

Description

technical field [0001] The present application relates to the technical field of chip packaging, and in particular, to a chip packaging method, a chip packaging body and an electronic device. Background technique [0002] As a kind of advanced packaging, FOPLP (fan-out board-level packaging) technology has been widely used in discrete devices. The fan-out board-level packaging area is smaller, and there is no substrate and interposer; The pin count density is also greater, which can better meet the end market's demand for chip miniaturization and high performance. [0003] In the current solution, the chip is soldered on the bottom pad, the strength of the bottom pad is too low, and there is a risk of the pad falling off when the product is soldered. As far as the current solution is concerned, there are certain defects in structural reliability. SUMMARY OF THE INVENTION [0004] The main technical problem to be solved by the present application is to provide a chip packa...

AI Technical Summary

Problems solved by technology

[0003] In the current solution, the chip is welded on the bottom pad, and the strength of the bottom pad is too low. There is a risk of the pad falling off when the product is soldered. As far as the current solution is concerned, there are certain defects in the structural reliability.

Images