Method, equipment and medium for realizing data arrangement

Abstract

The embodiment of the invention relates to a method and device for achieving data arrangement and a medium, and the method comprises the steps that first auxiliary data and second auxiliary data are obtained based on the thread count of a thread group and the data arrangement requirement; shifting the data in the first register, the first auxiliary data, the data in the second register and the second auxiliary data to a transfer register; extracting the data in the transfer register based on the address of the transfer register so as to obtain first data, second data, third data and fourth data; determining a mapping parameter based on the thread count of the thread group and the data arrangement requirement; and based on the mapping parameter, mapping the third data to the first register and mapping the fourth data to the second register, thereby realizing data arrangement in the registers. Therefore, data arrangement among a plurality of registers can be realized more quickly under the condition that the shared memory address is not calculated.

Description

Technical field [0001] Embodiments of the present disclosure relate in general to the processor field, and more particularly relate to a method for implementing data arrangement, computing devices and computer-readable storage media. Background [0002] In general, in general-purpose computing on graphicsprocessing units (GPGPUs), fast Fourier (FFT) operations with inputs as real numbers and outputs as complex numbers (R2C) are usually involved. The operation requires a sequence of real numbers of the original input (for example, parity rearrangement) to be rearranged into a new sequence of complex numbers. This involves arranging data between groups of threads (warps) between different registers. Permutation operations rely on data interaction between thread groups. [0003] The way data interacts between existing thread groups is primarily through shared storage. The system calculates the corresponding shared memory address according to the index of different thread data, and t...

AI Technical Summary

Problems solved by technology

This method increases the read delay of the instruction and wastes the data bandwidth of the instruction memory.

In addition, the index calculation of the shared memory is more complex and needs to be converted into additional calculations for the corresponding addresses

[0004] To sum up, the disadvantages of the traditional scheme for realizing data arrangement are that: the calculation operation of complex shared memory index address translation is added, and at the same time, the read and write operations of shared memory have a long delay, which affects program performance

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