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Signal acquisition method and chip verification platform

A verification platform and signal acquisition technology, applied in special data processing applications, CAD circuit design, etc., can solve problems such as omissions and high time costs, and achieve the effects of avoiding signal omissions, saving time costs, and improving chip verification and debugging efficiency

Pending Publication Date: 2022-03-25
新华三半导体技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, this application provides a signal acquisition method and a chip verification platform to solve the problem of high time cost caused by recompilation caused by trigger signal omission during chip verification

Method used

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  • Signal acquisition method and chip verification platform
  • Signal acquisition method and chip verification platform
  • Signal acquisition method and chip verification platform

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Embodiment Construction

[0025] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application.

[0026] The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and al...

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Abstract

The invention provides a signal acquisition method and a chip verification platform. The method comprises the following steps: when an exception occurs in a process of running a bit stream file of a to-be-tested design of a chip, recording a time point when the exception occurs by utilizing a clock counting module in the bit stream file; in the abnormal debugging process, a clock control module is used for controlling the to-be-tested design to run in a first running time period, and the right side endpoint value of the first running time period is not larger than the time point; when the running duration of the to-be-tested design reaches the first running time period, controlling the to-be-tested design to run in a second running time period; and in the operation process of the to-be-tested design in the second operation time period, the clock control module is utilized to control the signal acquisition module to acquire signals needing to be observed in the abnormal debugging process according to a single-cycle mode.

Description

technical field [0001] The present application relates to the technical field of chip design, in particular to a signal acquisition method and a chip verification platform. Background technique [0002] When verification is performed on the chip prototype verification platform, the available debugging means are limited when problems occur during the verification process. It is usually to set the trigger signal, that is, add the signal list to be collected before compiling, and then set the trigger signal at runtime. When the trigger condition is met, the signal acquisition module can collect the signal of a period of time before and after the trigger condition and restore Create a waveform to analyze the problem with that waveform. However, in this method, the trigger signal needs to be set before compilation. Once there is an omission, it needs to be recompiled, which not only requires more time cost, but also needs to consider the platform resources, the number of collect...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33
CPCG06F30/33
Inventor 孙磊邓小涛
Owner 新华三半导体技术有限公司
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