Automatic layout method and device based on Euler path algorithm

An Euler path and automatic layout technology, which is applied in computing, computer-aided design, CAD circuit design, etc., can solve the problem of low efficiency of integrated circuits, achieve the effect of automatic layout, reduce the area occupied by the layout, and reduce the time

Pending Publication Date: 2022-03-08
TSINGHUA UNIV
View PDF0 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present application provides an automatic layout method, device and storage medium based on the Euler path algorithm, so as to at least solve the technical problem of low efficiency of integrated circuit design in the related art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Automatic layout method and device based on Euler path algorithm
  • Automatic layout method and device based on Euler path algorithm

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] figure 1 It is a schematic flowchart of an automatic layout method based on the Euler path algorithm provided according to an embodiment of the present application, such as figure 1 As shown, can include:

[0031] Step 101 , acquiring the MOS tubes to be placed, and acquiring characteristic parameters of the MOS tubes to be placed.

[0032] Wherein, in the embodiment of the present application, the characteristic parameter of the MOS transistor may include: the gate width of the MOS transistor.

[0033] Step 102: Classify the MOS transistors to be placed according to the characteristic parameters to obtain multiple MOS transistor groups, wherein the MOS transistors in each MOS transistor group have the same width.

[0034] Wherein, in the embodiment of the present application, the above characteristic parameters of the MOS transistor may further include: a finger of the MOS transistor. And, in the embodiment of the present application, before classifying the MOS tran...

Embodiment 2

[0053] further, figure 2 It is a schematic structural diagram of an automatic layout device based on the Euler path algorithm provided according to an embodiment of the present application, as shown in figure 2 As shown, can include:

[0054] The obtaining module 201 is used to obtain the MOS tube to be placed, and obtain the characteristic parameters of the MOS tube to be placed;

[0055] The classification module 202 is used to classify the MOS transistors to be placed according to the characteristic parameters to obtain a plurality of MOS transistor groups, wherein the MOS transistors in each MOS transistor group have the same width;

[0056] The judging module 203 is used for respectively grouping the gate sequences of the MOS transistors in the MOS transistors, using the drain and source of the MOS transistors as the nodes of the graph theory, and judging whether the nodes of the graph theory constitute an Euler path. The nodes of the path are characterized by the int...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

According to the automatic layout method and device based on the Euler path algorithm and the storage medium provided by the invention, the MOS transistors to be placed can be classified according to the characteristic parameters of the MOS transistors to be placed to obtain a plurality of MOS transistor groups, and then the gate sequences of the MOS transistors in each group of MOS transistors are classified by taking the drain electrodes and the source electrodes of the MOS transistors as the nodes of the graph theory; whether the nodes of the graph theory form an Euler path or not is judged, if the nodes of the graph theory do not form the Euler path, preset components are added to the nodes with odd degrees in the graph theory so that the nodes which do not form the Euler path can be converted into the nodes forming the Euler path, and then the MOS transistors are placed according to the arrangement sequence in the formed Euler path. And forming a plurality of MOS tube grouping sequences after placement. According to the method provided by the invention, the automatic layout of the MOS tube is realized, so that the time required for designing the layout of the MOS tube by manually considering the integrated circuit is reduced, meanwhile, the active region of the MOS tube is ensured to be correctly shared, the layout occupied area is reduced, and the design period of the integrated circuit is shortened.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to an automatic layout method, device and storage medium based on the Euler path algorithm. Background technique [0002] The MOS transistor is a key component of the current integrated circuit, and the MOS transistor also needs to be laid out, and the MOS transistor needs to pay attention to the sharing of the active area when laying out the MOS transistor. [0003] In the related art, the layout of the MOS transistors requires an integrated circuit engineer to check whether the source and the gate of the MOS transistors are consistent and then manually place them, which makes the efficiency of the integrated circuit design low. Contents of the invention [0004] The present application provides an automatic layout method, device and storage medium based on the Euler path algorithm, so as to at least solve the technical problem of low efficiency of integrate...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392G06F30/398G06F115/06
CPCG06F30/392G06F30/398G06F2115/06
Inventor 叶佐昌王燕秦仟
Owner TSINGHUA UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap