Chip research and development method, system and device and storage medium

Abstract

The invention provides a chip research and development method, system and device and a storage medium. The method comprises the following steps: generating an SPEC file according to a chip architecture, generating a register conversion circuit code according to the SPEC file, putting the register conversion circuit code into a storage server, and writing a register conversion circuit index into a resource directory; reading a register conversion circuit code based on the register conversion circuit index, performing grammar check on the register conversion circuit code, and judging whether a grammar error exists in the register conversion circuit code or not; responding to the condition that no grammar error exists in the register conversion circuit code, performing logic synthesis according to the register conversion circuit code to generate a netlist, putting the netlist into a storage server, and writing a netlist index into a resource directory; and reading the netlist based on the netlist index, and performing formalized verification and time sequence analysis on the netlist. The resource utilization maximization can be realized, and the research and development efficiency is improved.

Description

technical field [0001] This field relates to the field of chip research and development, and more specifically refers to a method, system, device and storage medium for chip research and development. Background technique [0002] Since chip research and development is a process from scratch, from market demand analysis to overall architecture design, from the generation of the first version of RTL (register-transfer level, register conversion circuit), to RTL spyglass grammar check, RTL simulation (Simulation verification), RTL DC (design compiler, logic) comprehensively generates netlist netlist, netlist cdc check, netlist and RTL formality comparison, netlist simulation, netlist dft (sketch) check, to the later stage Static timing analysis, timing closure until tape-out. This cycle involves many EDA (Electronic Design Automation, electronic design automation) tools. Each EDA tool has different requirements for server resources, and EDA tool resource requirements are also ...

AI Technical Summary

Problems solved by technology

The prior art has the following defects: 1. The allocation of server resources corresponding to EDA software resources is chaotic; 2. For the RTL, DOC (document, file), netlist and other resources in the entire development cycle, the resources such as RTL, DOC (document, file), and netlist are randomly stored, and redundant storage causes waste of server resources.

Images