Clock synchronization system and method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a clock synchronization system and method, electronic equipment and a storage medium, and relates to the field of clock synchronization. The system comprises a master module and a slave module, which are in step-by-step communication connection; the master module is used for generating source data and sending the source data to the slave module, the source data comprises source information and a source clock signal; the slave module is used for receiving and analyzing the source data and obtaining the source clock signal; the slave module is also used for updating the slave clock signal to be synchronized with the source clock signal, adding the slave information into the source data, generating slave data and sending the slave data to the master module. According to the invention, the source clock signal is obtained, and the slave clock signal is updated according to the source clock signal, thereby achieving the purpose of clock signal synchronization. Besides, the communication mode of the system is greatly simplified, and the difficulty of development and design is reduced.

Description

technical field [0001] The present invention relates to the field of clock synchronization, in particular to a clock synchronization system, method, electronic equipment and storage medium. Background technique [0002] With the continuous development of science and technology, programmable logic devices are widely used in various fields. The system composed of programmable logic devices can be used for parallel computing. Its design and operation depend on clock signals. Every programmable logic device The change of a signal is closely related to the clock signal, so the difficulty in designing parallel computing lies in the control of the clock signal. [0003] In the prior art, various bus protocols are often used to adjust the clock signal to synchronize the programmable logic devices. However, the communication mechanism of the existing bus protocols is quite complicated, which greatly increases the difficulty of development and design. Contents of the invention [0...

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Problems solved by technology

[0003] The existing technology often adjusts the clock signal through various bus protocols to synchronize the programmable logic devices. However, the communication mechanism of the existing bus protocols is quite complicated, which greatly increases the difficulty of development and design.

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