Clock-error estimation for two-clock electronic device

Abstract

Clock-error estimation for a two-clock electronic device. An implementation method is used for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period and wherein the difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of European Patent Application No. 20305147.9 filed February 17, 2020, which is hereby incorporated by reference. technical field [0003] The present disclosure relates generally to operating dual clock electronics and, in particular, to finding an estimate of a clock error of one of two clocks of a dual clock electronics. Furthermore, the present disclosure relates to implementing such clock error estimation into a positioning system, particularly an ultra-wideband (UWB) positioning system based on communicating UWB signals between mobile tag devices and stationary devices. For example, the present disclosure relates to efficiently controlling timing within such UWB communications, particularly with respect to the sequence of exchanging UWB signals within a UWB communications frame. Background technique [0004] For the concepts disclosed herein, an electronic device includes two...

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Problems solved by technology

However, during some time intervals, those systems can only use low-power clocks to save power

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