Erasing verification method and device of storage unit, computer equipment and storage medium

A technology for erasing verification and storage units, which is applied in the field of data processing, and can solve problems such as over-erasing, increasing the probability of reading errors, and the decline of cyclic erasing and writing capabilities, and achieve the effect of reducing loss and reducing the probability of reading errors

Pending Publication Date: 2021-06-08
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Among them, the word line simultaneous verification method is prone to over-erasing phenomenon, resulting in a large number of interface defects in the storage device during the cyclic erasing process, which in turn leads to the decline of the cyclical erasing capability
In the initial use of the word line alternate verification method for memory devices, due to the shallow erase depth, the coupling between the programmed unit and the erased unit is prone to occur during programming, which increases the probability of read errors

Method used

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  • Erasing verification method and device of storage unit, computer equipment and storage medium
  • Erasing verification method and device of storage unit, computer equipment and storage medium
  • Erasing verification method and device of storage unit, computer equipment and storage medium

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Embodiment 1

[0023] figure 1 A flow diagram of an erase verification method of a memory cell in the first embodiment of the present invention, the present embodiment can be applied to the case where the memory unit is erased after erasing, and the method can be provided by the present invention. The erase verification device of the unit is performed, and the device can be implemented in software and / or hardware, and generally integrated into electronic devices, for example, a terminal device or server or the like. Such as figure 1 As shown, the method of this embodiment includes:

[0024] S110, when it is determined that the erase verification requirements of the memory block are generated, the current erase cycle statistics of the storage block is obtained.

[0025] Specifically, in the memory, the memory block is the smallest erase unit. Typically in the memory, multiple storage units form a page (PAGE), a plurality of pages form a memory block, where the page is the smallest read / write...

Embodiment 2

[0053] figure 2 The flow chart of the erase verification method of the memory unit of the second embodiment of the present invention, the present embodiment is optimized by the above embodiment, and the query is the erase verification method that matches the current erase cycle statistics. The statistical result is compared to the preset at least one erase cycle number threshold with the preset at least one erasing cycle; in accordance with the comparison result, in the corresponding relationship between the preset comparison and the erase verification method, the current Erase the erase verification method of the loop statistics. At the same time, the erasing verification method that matches the current erase cycle statistics from the preset comparison result in the corresponding relationship of the preset comparison method and the current erase cycle statistics is queried, and the current erase cycle statistics A smaller than the first cycle number threshold, determining that t...

Embodiment 3

[0063] image 3 A schematic diagram of an erase verification device of a memory cell in the third embodiment of the present invention. The third embodiment is a respective device of the erasing verification method of the memory cell provided by the above embodiment of the present invention, which can be implemented in software and / or hardware, and generally integrated into electronic devices, for example, computer equipment, etc.

[0064] Accordingly, the apparatus of the present embodiment can include:

[0065] The current erase cycle statistical result acquisition module 310 is used to obtain the current erase cycle statistics of the storage block when determining the erase verification requirements of the memory block;

[0066] The erase verification module 320 is used to query the erase verification method that matches the current erase cycle statist results to erase each memory cell per memory cell.

[0067] The embodiment of the present invention performs erase verification ...

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Abstract

The embodiment of the invention discloses an erasure verification method and device of a storage unit, computer equipment and a storage medium. The method comprises the steps that when determining that an erasure verification requirement for a storage block is generated, acquiring a current erasure cycle statistical result of the storage block; and querying an erasure verification mode matched with the current erasure cycle statistical result to perform erasure verification on each storage unit in the storage block. According to the embodiment of the invention, the erasing loss of the flash memory can be reduced while the erasing verification is considered.

Description

Technical field [0001] Embodiments of the present invention relate to the field of data processing, and more particularly to the erase verification method, apparatus, computer device, and storage medium of memory cells. Background technique [0002] At present, non-volatile storage products have electronic programming and erase. For example, in the field of flash memory, flash memory is based on semiconductor memory. It can still retain internal information and online erasing after power-down. The current flash memory is mainly divided into two categories, including NOR flash memory. And NAND flash memory, where NOR FLASH implements the device programming with the heat electron injection mechanism, and the tunneling effect is used to achieve erasure, while the programming and erasing of NAND Flash are implemented by tunnel effects. [0003] Specifically, the physical structure of NAND Flash determines its erase operation to erase, ie, multiple memory cells included in a memory bl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/34G11C16/16
CPCG11C16/16G11C16/3472G11C16/3477
Inventor 林子曾刘会娟金浩妮潘荣华
Owner GIGADEVICE SEMICON (BEIJING) INC
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