Reconfigurable floating point multiply-add operation unit and method suitable for multi-precision calculation

Abstract

The invention discloses a reconfigurable floating point multiply-add operation unit and method suitable for multi-precision calculation, and the method comprises the steps: dividing mantissas of floating points with different precision through employing a unified method, and obtaining a plurality of bit segments; and calling different numbers of same-type unit multipliers to achieve multiplication of a plurality of bit segments in one period and output corresponding products, and then performing shift addition operation on the products to obtain a multiply-accumulate operation result of the floating-point number. The problem of bit redundancy is avoided by adopting a unified mantissa division scheme, the hardware utilization rate is improved by adopting a unified unit multiplier, and the multiply-accumulate operation of half-precision floating-point numbers, the multiply-accumulate operation of single-precision dot product floating-point numbers and the multiply-accumulate operation of double-precision floating-point numbers can be achieved. The problems of bit redundancy, low hardware utilization rate and the like of an operation method supporting multi-precision floating point multiplication in the prior art are solved.

Description

technical field [0001] The invention relates to the field of digital circuits, in particular to a reconfigurable floating point multiplication and addition operation unit and method suitable for multi-precision calculation. Background technique [0002] With the rapid development and wide application of scientific computing and machine learning training, multiplication units that can support floating-point data processing have emerged as the times require. The number of input bits of conventional fixed-point multipliers is fixed, which cannot meet the requirements of multi-precision calculations, so a method to support multi-precision floating-point multiplication operations has emerged. However, due to the need for a variety of mantissa division schemes and the need to separate the generated product into two parallel parts with zero padding, the existing calculation methods that support multi-precision floating-point multiplication have precision loss, bit redundancy, and h...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a reconfigurable floating-point multiplication and addition operation unit suitable for multi-precision calculations in view of the above-mentioned defects of the prior art The invention and method aim to solve the problems that the operation method supporting multi-precision floating-point multiplication operation in the prior art will generate bit redundancy and low hardware utilization rate, etc.

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