A method and device for realizing 32-bit integer division with high precision and low delay

Abstract

The present invention provides a method and device for realizing 32-bit integer division with high precision and low delay, including the following steps: S1, the dividend and the divisor are input to the zero judgment unit. If the dividend is 0, the quotient directly outputs 0, and the scaling factor is 0. ; S2, output the dividend and the divisor of 1, input the symbol extraction module, and output the sign of the quotient and the modulus of the dividend and the divisor. In the present invention, the initial value of Newton iteration is realized by CORDIC with fewer iterations, only addition and shift operations, low resource consumption, and convenient hardware implementation. Through the scaling module, the dividend and divisor are scaled to the same amplitude position, reducing the The calculation bit width reduces the need for the number of iterations, reduces the operation cycle, and adds a Newton iteration. At the cost of a small number of arithmetic units and delays, the calculation accuracy is increased. The output result is in the form of a quotient plus a scaling factor, which effectively guarantees the The accuracy, and the output bit width is small, which is convenient for subsequent use. The error is less than one thousandth.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a method and device for realizing 32-bit integer division with high precision and low delay. Background technique [0002] In the field of digital signal processing, 32-bit integer dividers are often used, such as in signal normalization and channel estimation, but the existing 32-bit integer dividers have the following disadvantages: [0003] 1. Existing division schemes often use derivative division, SRT method, addition and subtraction alternate method, CORDIC method, etc. The operation cycle of these methods often increases a lot with the increase of the number of digits, which wastes power consumption. [0004] 2. With the increase of the data bit width, the middle bit width of the arithmetic unit often becomes larger and larger, occupying more storage space. [0005] 3. In order to ensure performance, the bit width of the output result is large, and the r...

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Problems solved by technology

[0003] 1. Existing division schemes often use derivative division, SRT method, addition and subtraction alternate method, CORDIC method, etc. The operation cycle of these methods often increases with the number of digits increasing, wasting power consumption

[0004] 2. With the increase of the data bit width, the middle bit width of the arithmetic unit is often larger and larger, occupying more storage space

[0005] 3. In order to ensure performance, the bit width of the output result is large, and the resource overhead of subsequent addition and multiplication is relatively large

[0006] 4. Reciprocal division, Newton iteration plus one multiplication is commonly used to realize a / b, but there are generally two sources of initial value of Newton iteration, look-up table method or Tylor expansion, both of which require storage space, and Tylor expansion Requires additional multiplication and addition, consuming resources

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