A data processing method and device

Abstract

The invention discloses a data processing method and equipment. Firstly, a home bus signal including a first logic sub-signal is obtained. The first logic sub-signal includes a low-level signal and a first high-level signal. When the duty ratio data of the flat signal and the duty ratio data of the first high-level signal are determined, the first sampling point for collecting the low-level signal is determined according to the determined duty ratio data and the preset sampling point selection rule. point, the second sampling point for collecting the first high-level signal, and then the low-level signal can be collected according to the first sampling point, and the first high-level signal can be collected according to the second sampling point, and then according to the preset The signal conversion rules determine the first target signal corresponding to the first logic sub-signal, so that even when the duty ratio data changes, the low-level signal and the first high-level signal can still be determined to avoid The change of the air ratio leads to the problem of acquisition error and realizes successful communication.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a data processing method and device. Background technique [0002] The home bus home hus signal includes a logic "0" signal and a logic "1" signal, see eg figure 1 The encoding method of the homehus signal shown, when the transmission frequency is 10KHz, the logic "1" signal is a high-level signal with a pulse width of 100us, and the logic "0" signal includes: a low-level signal with a pulse width of 50us and a pulse A high-level signal with a width of 50 us, and in the logic "0" signal, the duty cycles of the low-level signal and the high-level signal are 50% respectively. [0003] When sending the home hus signal, there may be a delay from the logic "0" signal to the logic "1" signal, which may cause the pulse width of the high-level signal and the low-level signal in the logic "0" signal Not equal, that is, the duty cycle of the high-level signal and low-level signal ...

AI Technical Summary

Problems solved by technology

[0003] When sending the home hus signal, there may be a delay from the logic "0" signal to the logic "1" signal, which may cause the pulse width of the high-level signal and the low-level signal in the logic "0" signal Not equal, that is, the duty cycle of the high-level signal and low-level signal in the logic "0" signal is not 50%, and then when receiving the home bus signal, due to the change of the duty cycle, the acquisition logic When there are high-level signals and low-level signals in the "0" signal, acquisition errors will occur, resulting in communication failures

Images