Compensation method and device for bit line leakage current of static random access memory

A static random and compensation method technology, applied in static memory, digital memory information, information storage and other directions, can solve the problems of affecting the readout rate, increase the area of ​​SRAM cells, etc., to improve the circuit working speed, reduce the reading working time, improve the The effect of discharge rate

Inactive Publication Date: 2020-06-19
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, increasing the compensation transistor in the SRAM unit will increase the area of ​​the SRAM unit, and the use of capacitance compensation will increase the load capacitance of the bit line. At the same time, the current sampling sequence is required, which affects the readout rate.

Method used

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  • Compensation method and device for bit line leakage current of static random access memory
  • Compensation method and device for bit line leakage current of static random access memory

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Embodiment 1

[0033] like figure 2 As shown, when reading the C1 cell, the bit line is precharged to a high potential, and a leakage current will be formed between the bit line and the "0" node inside the SRAM cell, and the leakage current will affect the discharge current on the bit line. As the scale of the circuit increases, more and more SRAM cells are connected to the bit line, and the cells that generate leakage current will also increase. When the total leakage current is large enough that the discharge current on the bit line BL is close to or even greater than When the discharge current on BL_n, it will cause read failure. Assuming that each bit line of the SRAM circuit is connected with N SRAM cells, where n cells on BL will generate leakage current, then N-n cells on BL_n will generate leakage current. The leakage current generated by each cell is I lkg , the turn-on current is I on . While reading the SRAM cell C 1 During the process, the total discharge current on the bit...

Embodiment 2

[0047] This embodiment provides a compensation device for bit line leakage current of SRAM, including: at least one compensation module; the compensation module includes:

[0048] A voltage sampling circuit, which collects the discharge currents of two adjacent bit lines; optionally, the voltage sampling circuit is used to sample the voltages of two adjacent bit lines and calculate the rate of voltage change with time, so as to obtain the The discharge current of two adjacent bit lines is described.

[0049] A signal control circuit, configured to receive information collected by the voltage sampling circuit and send a control signal;

[0050] The voltage feedback circuit is used to control the decrease of the voltage of the bit line with a larger discharge current among the two adjacent bit lines, and / or control the increase of the voltage of the bit line with a smaller discharge current among the two adjacent bit lines.

[0051] For this embodiment, there are three optional...

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Abstract

The invention provides a compensation method for bit line leakage current of a static random access memory. The compensation method comprises the following steps: collecting discharge current of two adjacent bit lines; and controlling the voltage of the bit line with relatively large discharge current in the two adjacent bit lines to be reduced, and/or controlling the voltage of the bit line withrelatively small discharge current in the two adjacent bit lines to be increased. According to the compensation method for the bit line leakage current of the static random access memory, less time isneeded when the SA can detect the voltage, the read working time is shortened, and the working speed of the circuit is increased. In the same read clock window, the SA can detect a larger voltage difference.

Description

technical field [0001] The invention relates to the technical field of compensation for bit line leakage current of SRAM, in particular to a compensation method and device for bit line leakage current of SRAM. Background technique [0002] As a typical storage structure, Static Random Access Memory (SRAM) has been widely used in Logic Large Scale Integration (LSI). This is because SRAM has the advantages of fast operation speed and low static power consumption, and at the same time, SRAM can use the same manufacturing process as logic circuits. As an important part of logic LSI, SRAM will directly affect the performance and yield of the entire circuit. As the scale of the circuit becomes larger and the process node becomes more advanced, it will bring side effects to the circuit. One of the biggest problems is that as the process node decreases, the leakage of the bit line increases, and the increase of leakage will affect the operation of the SRAM. , especially the discha...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C5/14G11C7/12G11C11/419
CPCG11C5/147G11C7/12G11C11/419
Inventor 翟永成霍杰
Owner SHENZHEN PANGO MICROSYST CO LTD
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