Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for packaging densely-arranged semiconductor chips for Internet of Things terminal

A technology of IoT terminal and packaging method, which is applied in the direction of semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., and can solve the problems that the connection between the chip and the pin is easy to be torn off, the chip is damaged, and the chip is pulled. , to achieve the effect of good fixing effect, simple structure and good bonding performance

Active Publication Date: 2020-05-01
袁晓华
View PDF5 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, there are many ways to package semiconductor chips, but they are similar. Most of the connection methods between the chip and the pins are directly connected. Since the pins are extended to the outside of the package, the pins will be accidentally pulled during installation or transportation. pins, it is easy to tear the chip inside the package, and the connection between the chip and the pin is also easy to be torn off. In addition, when the chip is finally plastic-packed, the plastic shell must press the chip. If the control is not good, it is easy to cause damage to the chip.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for packaging densely-arranged semiconductor chips for Internet of Things terminal
  • Method for packaging densely-arranged semiconductor chips for Internet of Things terminal
  • Method for packaging densely-arranged semiconductor chips for Internet of Things terminal

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] see Figure 1-7 , a packaging method for densely arranging semiconductor chips for Internet of Things terminals, including a lower housing 1, see figure 1 , the upper surface of the lower casing 1 is provided with a placement groove 5, and the upper surface of the lower casing 1 is fixedly connected with two sets of conductive columns 2, and the two sets of conductive columns 2 are respectively located on both sides of the placement groove 5, and the lower casing 1 There is a perforation 3 inside, the shape of the perforation 3 is L-shaped, and the lower opening of the perforation 3 is filled with insulating glue 15, because there is a corner on the L-shaped perforation 3, so that when the leaked pin 4 is involved At this time, the hole wall at the corner can play a counterweight role to prevent the conductive column 2 from being affected, the insulating glue 15 plays the role of insulation, and also plays the role of sealing, and the perforation 3 is located below the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for packaging densely-arranged semiconductor chips for an Internet of Things terminal and belongs to the semiconductor packaging field. The method for packaging densely-arranged semiconductor chips for the Internet of Things terminal is characterized in that a placement groove is formed in an upper surface of a lower shell, the upper surface of the lower shell is fixedly connected with two groups of conductive columns, the two groups of conductive columns are respectively positioned on two sides of the placement groove, a through hole is formed in the lower shell, the through hole is formed below the conductive columns, a pin is placed in the through hole, an upper end of the pin is fixedly connected with the conductive columns, adhesive is adhered to the bottom of the placement groove, a chip is placed in the placement groove, a lower end of the chip is bonded with the adhesive, and an upper surface of the chip is connected with the conductive columnsthrough a plurality of wires. The method is advantaged in that indirect connection between the chip and the pins can be realized, shaking or damage of the chip due to the fact that the pin drags the chip can be avoided, an elastic packaging mode is adopted during plastic packaging, so the fixing effect can be achieved, and the chip cannot be damaged.

Description

technical field [0001] The present invention relates to the field of semiconductor packaging, and more specifically, to a packaging method for densely arranging semiconductor chips used in Internet of Things terminals. Background technique [0002] Packaging technology is necessary and crucial for the chip, because the chip must be isolated from the outside world to prevent impurities in the air from corroding the chip circuit and causing electrical performance degradation. On the other hand, the packaged chip is also more It is convenient for installation and transportation, because the packaging technology directly affects the performance of the chip itself and the design and manufacture of the PCB connected to it, so it is very important. [0003] At present, there are many ways to package semiconductor chips, but they are similar. Most of the connection methods between the chip and the pins are directly connected. Since the pins are extended to the outside of the package...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/055H01L23/24H01L23/48
CPCH01L23/055H01L23/24H01L23/48
Inventor 袁晓华
Owner 袁晓华
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products