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Interface time sequence calibration method and device

A timing calibration and interface technology, applied in the field of communications, can solve the problem of small chip interface window margin, and achieve the effect of maximizing the effective window margin

Pending Publication Date: 2019-12-27
AMOLOGIC (SHANGHAI) CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Aiming at the problem of small interface window margin of existing chips, a method and device for interface timing calibration aiming at selecting the best timing parameters according to different chips are now provided

Method used

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  • Interface time sequence calibration method and device
  • Interface time sequence calibration method and device

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Embodiment Construction

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0036] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0037] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0038] Such as figure 1 As shown, this embodiment provides a method for calibrating interface timing, which is ...

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Abstract

The invention discloses an interface time sequence calibration method and device, and belongs to the technical field of communication. The interface time sequence calibration method is applied to an interface coupled to an application layer and a physical layer; the application layer sends a data packet to the physical layer by adjusting the stepping of the application layer for receiving a clocksignal, and the data packet looped back by the physical layer is acquired, so that the effectiveness of the clock signal is judged according to the data packet received by the application layer; the phase of the received target clock is obtained according to the clock phase effective range of the clock signal, thereby realizing selection of the optimal clock time sequence parameter according to different chips, and maximizing the effective window margin of the interface.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a method and device for calibrating interface timing. Background technique [0002] The existing chip interface is greatly affected by the manufacturing deviation of the chip, and there is a large deviation between the data of the chip interface and the clock timing. The chip generally adopts fixed timing parameters, and the effective window margin is relatively small, resulting in product yield. Poor question. Contents of the invention [0003] Aiming at the problem of small interface window margin in existing chips, an interface timing calibration method and device are provided to select the best timing parameters according to different chips. [0004] A method for calibrating interface timing, applied in an interface coupled to an application layer and a physical layer, wherein the physical layer adopts a loopback mode, comprising the steps of: [0005] Adjust the s...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4072G06F13/4204G06F2213/0004
Inventor 张西锋段琪王卓邓海东孙顺清
Owner AMOLOGIC (SHANGHAI) CO LTD
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