LDO-based FPGA loading configuration problem checking method

Abstract

The invention discloses an LDO-based FPGA loading configuration problem checking method, and relates to an LDO-based FPGA loading configuration problem checking method, which solves the problem of FPGA configuration loading failure caused by configuration starting at a latent conduction stage and a DCDC output voltage rising stage in the existing imaging application. The method comprises the following steps: checking a JTAG connection failure problem; checking the failure of the flash data program; checking flash loading failure; checking power supply capability based on an LDO power supply; and the like. The method aims to avoid configuration loading failure caused by configuration starting in a latent conduction stage and a DCDC output voltage rising stage in an imaging application. An LDO power supply mode that an IO of an FPGA is powered on first and then powered on is provided, and the power supply capacity of the LDO is selected through the loading current of the FPGA and a filter capacitor, so that the rise time of power supply of the FPGA core is ensured to meet the configuration requirement. Aiming at possible problems of different application modes, different inspection methods are designed. According to the method, the problem can be quickly positioned, and the troubleshooting cost is reduced. Design errors can be found in advance, and the possibility of reworking isreduced.

Description

technical field [0001] The invention relates to an LDO-based FPGA loading configuration problem checking method, in particular to a CMOS imaging application-based LDO FPGA loading configuration problem checking method. Background technique [0002] For imaging FPGA applications based on CMOS image sensors, the configuration data inside the FPGA can be directly downloaded to the FPGA through the JTAG port. Since the configuration data burned in through the JTAG port is volatile after power-off, it can also be downloaded to the non-volatile flash through the JTAG port before power-on and load the configuration; or it can be burned through the programmer first. Go to the prom memory and then power on and load the configuration. In common applications, the imaging controller is powered on first, and then controls the FPGA-centered imaging unit to be powered on and generates control signals. Since the imaging controller is powered on first, the sneak pass of the control signal ...

AI Technical Summary

Problems solved by technology

[0003] The present invention provides an LDO-based checking method for FPGA loading and configuration problems in order to solve the problem of FPGA configuration loading failure caused by sneak-through and DCDC output voltage rising stage start-up configuration in existing imaging applications

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