Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method and system for expanding number of bus channels based on GPIO

A technology for expanding the bus and channels, applied in the field of expanding the number of bus channels based on GPIO, can solve the problems of low system reliability and low access efficiency, simplify access procedures, avoid read and write operation delays, and improve reliability and stability Effect

Inactive Publication Date: 2019-07-05
SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
View PDF5 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present application provides a method and system for expanding the number of bus channels based on GPIO, so as to solve the problems of low system reliability and low access efficiency of I2C master devices to slave devices in the method of extending the I2C bus in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method and system for expanding number of bus channels based on GPIO
  • Method and system for expanding number of bus channels based on GPIO
  • Method and system for expanding number of bus channels based on GPIO

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] see figure 1 , figure 1 A method for expanding the number of bus channels based on GPIO provided by the embodiment of the present application, the method mainly includes the following process:

[0031] S1: Use the GPIO of the master device to simulate multiple bus channels, any bus channel includes SCL signal and SDA signal.

[0032] In this embodiment, the bus channel includes an I2C channel or an SMBus channel. Taking the I2C channel as an example for the bus channel, the method of step S1 is: use the GPIO of the I2C master device to simulate multiple I2C channels, and any I2C channel includes SCL signal and SDA signal.

[0033] Since the method in this embodiment is common to the I2C bus and the SMBus bus, when implementing the method in this application, in most cases, the I2C bus and the SMBus bus may not be distinguished. The main difference between the two is that the bus frequency is different. The maximum bus frequency of SMBus is lower than the bus frequenc...

Embodiment 2

[0049] exist figure 1 with figure 2 On the basis of the illustrated embodiment see image 3 , image 3 It is a schematic structural diagram of a system for expanding the number of bus channels based on GPIO provided in the embodiment of the present application. Depend on image 3 It can be seen that the system for expanding the number of bus channels based on GPIO in this embodiment includes: a master device, multiple slave devices, multiple bus channels, and multiple pull-up resistors. Wherein, the master device is provided with multiple GPIOs, and the master device is connected to one or more slave devices through any bus channel. Any bus channel includes an SCL signal and an SDA signal, and the SCL signals in multiple bus channels are the same and the SDA signals are different. Each pull-up resistor is matched with an SCL signal or an SDA signal. Specifically, the SDA signal in each bus channel is connected with a pull-up resistor. Since all bus channels share an SCL ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method and a system for expanding the number of bus channels based on a GPIO, and the method comprises the steps: using a GPIO of a main device to simulate a plurality of buschannels, and enabling any bus channel to comprise an SCL signal and an SDA signal; all the slave devices connected with the master device share one SCL signal, and each slave device adopts an independent SDA signal. The system provided by the invention comprises a main device, a plurality of slave devices, a plurality of bus channels and a plurality of pull-up resistors. A plurality of GPIOs arearranged in the master device, the master device is connected with one or more slave devices through any bus channel, any bus channel comprises an SCL signal and an SDA signal, the SCL signals in theplurality of bus channels are the same, and each pull-up resistor is matched with one SCL signal or one SDA signal. Through the method and the device, the stability and reliability of data operationcan be improved, the access program of the master device to the slave device is simplified, and the data transmission efficiency is improved.

Description

technical field [0001] The present application relates to the technical field of server system design, in particular to a method and system for expanding the number of bus channels based on GPIO (General Purpose Input / Output). Background technique [0002] The development of the I2C (Inter-Integrated Circuit, a bus used to connect microcontrollers and their peripherals) bus is not limited to the bus transmission rate, but also reflected in the expansion of the number of channels. With the development of I2C bus technology, more and more I2C devices are used in various electronic products. Therefore, in server system design, how to expand the I2C channel is an important technical issue. [0003] At present, a method commonly used in the industry to expand the I2C channel is to use the standard usage method provided in the I2C bus specification, that is, to hang multiple devices under the same I2C channel at the same time. That is to say, the CPU is used as the I2C master dev...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38G06F13/42
CPCG06F13/382G06F13/4282
Inventor 韩威
Owner SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com