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Semiconductor device and method of forming the same

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve problems such as performance to be improved, meet the requirements of process design, and avoid the effect of too small width

Active Publication Date: 2022-03-18
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of semiconductor devices composed of fin field effect transistors in the prior art still needs to be improved

Method used

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  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same

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Effect test

Embodiment Construction

[0031] As mentioned in the background, semiconductor devices formed in the prior art have poor performance.

[0032] Figure 1 to Figure 3 It is a structural schematic diagram of the formation process of a semiconductor device.

[0033] refer to figure 1 , provide a semiconductor substrate 100, the semiconductor substrate 100 includes a first region A and a second region B, the second region B is adjacent to the first region A; an intrinsic fin 110 and a dummy fin 120 are formed, the intrinsic fin 110 Located on the first region A of the semiconductor substrate 100 , the dummy fin 120 is located on the second region B of the semiconductor substrate 100 .

[0034] refer to figure 2 , removing the dummy fin portion 120 .

[0035] refer to image 3 , after removing the dummy fin 120 , an isolation layer 130 is formed on the first region A and the second region B of the semiconductor substrate 100 , and the isolation layer 130 covers part of the sidewall of the intrinsic fin...

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Abstract

A semiconductor device and a method for forming the same, wherein the method includes: providing a semiconductor substrate, the semiconductor substrate includes a first region and a second region, the second region is adjacent to the first region; forming intrinsic fins and dummy fins, the intrinsic The characteristic fin is located on the first region of the semiconductor substrate, and the dummy fin is located on the second region of the semiconductor substrate; a first isolation layer is formed on the first region and the second region of the semiconductor substrate, and the first isolation layer covers the dummy fin A part of the sidewall of the intrinsic fin and a part of the sidewall of the intrinsic fin; a protective layer is formed on the surface of the intrinsic fin, and the area of ​​the intrinsic fin that is higher than the surface of the first isolation layer is covered by the protective layer; the dummy fin and the first isolation layer are removed. The first isolation layer in the second region; after removing the dummy fin and the first isolation layer in the second region and forming the protective layer, forming a second isolation layer on the second region of the semiconductor substrate. The method prevents the width of the intrinsic fin adjacent to the second region from being too small.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] MOS (Metal-Oxide-Semiconductor) transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; The source and drain doped regions in the semiconductor substrate on both sides of the pole structure. [0003] With the development of semiconductor technology, the ability of the traditional planar MOS transistor to control the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/08H01L29/10H01L29/78
CPCH01L21/823481H01L21/76224H01L29/6681H01L21/823431H01L21/02271H01L21/31053H01L21/31144H01L21/02164H01L21/31111H01L21/02337
Inventor 张城龙
Owner SEMICON MFG INT (SHANGHAI) CORP
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