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Forming method of 3D NAND memory

A 3DNAND, memory technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of storage structure failure, achieve the effect of preventing failure and reducing the width

Active Publication Date: 2019-05-28
YANGTZE MEMORY TECH CO LTD
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

[0004] In order to further increase the storage capacity, when forming the stack structure in the prior art, a multi-layer stack structure is usually formed, and each layer stack structure includes several alternately stacked sacrificial layers and isolation layers. In the multi-layer stack structure A channel hole is formed; a storage structure is formed in the channel hole, but this storage structure still has the problem of failure

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  • Forming method of 3D NAND memory
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  • Forming method of 3D NAND memory

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Embodiment Construction

[0031] As mentioned in the background, the existing multi-layer stacked 3D NAND memory has the problem of failure.

[0032] The study found that the location where the failure problem of multi-layer stacked 3D NAND memory generally occurs at the junction of the multi-layer stacked structure, please refer to figure 2 20 positions indicated by the dotted box in .

[0033] After further research, the specific reasons for the above problems are: Figure 1-2 It is a schematic diagram of the cross-sectional structure of the formation process of the 3D NAND memory according to an embodiment of the present invention. First, please refer to figure 1 , forming a first stack structure 211 on the semiconductor substrate 200, the first stack structure 211 includes a number of alternately stacked sacrificial layers 203 and insulating layers 204, the first stack structure 211 and the semiconductor substrate 200 can also be Form a buffer oxide layer 201 and a dielectric layer 202; etch th...

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Abstract

The invention discloses a forming method of a 3D NAND memory. The method comprises the steps of providing a semiconductor substrate, wherein a stacking structure is formed on the semiconductor substrate and comprises a plurality of sacrificial layers and isolation layers which are alternately stacked; the stacking structure is provided with a first channel hole and a second channel hole which communicate with each other, the second channel hole is aligned and deviated relative to the first channel hole, a step is formed at the junction of the first channel hole and the second channel hole, andthe first channel hole is filled with a sacrificial material layer; forming a side wall on the side wall of the second channel hole; etching the first channel hole to enable the width of the first channel hole to be widened and enable the width of the step to be reduced; forming charge storage layers on the side walls and the bottoms of the first channel hole and the second channel hole; forminga channel hole sacrificial layer on each charge storage layer; and sequentially etching the channel hole sacrificial layer and the charge storage layer on the bottom of the first channel hole to forman opening. The method provided by the invention prevents the charge storage layer at the step from being etched or damaged, thereby preventing the memory from failing.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a 3D NAND memory. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The manufacturing process of the existing 3D NAND memory includes: providing a substrate on which a stacked structure in which isolation layers and sacrificial layers are alternately stacked; etching the stacked structure to form an exposed substrate surface in the stacked structure channel hole; form a storage structure in the cha...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/1157H01L27/11573H01L27/11575H01L27/11582H10B43/35H10B43/27H10B43/40H10B43/50
Inventor 霍宗亮薛家倩
Owner YANGTZE MEMORY TECH CO LTD
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