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Data interaction method of heterogeneous multi-core processor, heterogeneous multi-core processor and terminal

A multi-core processor and data interaction technology, applied in the field of communication, can solve problems such as poor real-time performance and low communication efficiency between cores, and achieve the effects of ensuring reliability and integrity, shortening data interaction time, and fast interaction

Inactive Publication Date: 2019-05-10
UBTECH ROBOTICS CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the above problems, the present invention proposes a data interaction method for a heterogeneous multi-core processor, a heterogeneous multi-core processor and a terminal, by dividing and mapping the master-slave interaction data area in advance, and reading and writing the device by the master CPU. The CPU directly maps and reads and writes through the structure, which can solve the problems of low communication efficiency between cores and poor real-time performance in the existing technology

Method used

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  • Data interaction method of heterogeneous multi-core processor, heterogeneous multi-core processor and terminal
  • Data interaction method of heterogeneous multi-core processor, heterogeneous multi-core processor and terminal
  • Data interaction method of heterogeneous multi-core processor, heterogeneous multi-core processor and terminal

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Embodiment 1

[0038] Please also refer to figure 1 , figure 2 , image 3 and Figure 4 , this embodiment proposes a data interaction method for heterogeneous multi-core processors, which can be applied to heterogeneous multi-core processors and the like. In this embodiment, the heterogeneous multi-core processor includes a master CPU and at least one slave CPU, wherein the master CPU can run an operating system, and each slave CPU directly runs an engineering program. The data interaction method of the heterogeneous multi-core processor will be described in detail below mainly by taking a slave CPU as an example.

[0039] In this example, the figure 2As shown, the master CPU and the slave CPU of the heterogeneous multi-core processor can perform fast data interaction through a preset master read-slave write area and a preset master write-slave read area. Such as image 3 As shown, the creation process of the preset master read-slave write area and the preset master write-slave read ...

Embodiment 2

[0074] Please refer to figure 1 , based on the data interaction method in the above-mentioned embodiment 1, this embodiment proposes a heterogeneous multi-core processor, the heterogeneous multi-core processor includes a master CPU and at least one slave CPU, the master CPU with an operating system and each When data exchange is performed from the CPU, the data exchange method of the heterogeneous multi-core processors in the above-mentioned embodiment 1 is adopted, so it will not be described in detail here.

Embodiment 3

[0076] Based on the data interaction method in Embodiment 1 above, this embodiment proposes a terminal, the terminal includes a heterogeneous multi-core processor, and the heterogeneous multi-core processor includes a master CPU with an operating system and at least one bare-metal slave CPU. Wherein, the data interaction method in the above-mentioned embodiment 1 is adopted when the master CPU and each slave CPU perform data interaction, so it will not be described in detail here.

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Abstract

The invention discloses a data interaction method of a heterogeneous multi-core processor. The invention discloses a heterogeneous multi-core processor and a terminal. The heterogeneous multi-core processor comprises a master CPU with an operating system and at least one bare computer slave CPU, The method comprises the following steps that: a master CPU (Central Processing Unit) periodically executes a master-slave mode or reads data from a preset master-read slave-write area in an equipment driving mode when receiving an interrupt or mailbox message sent from the slave CPU, and writes the data required to be updated into the preset master-write slave-write area; and when receiving an interrupt or mailbox message sent by the master CPU, the slave CPU reads and processes the updated data from the preset master-write slave read area in a structural body read-write mode, and writes the processed data into the preset master-write slave read area. According to the technical scheme, secondary caching during data interaction between the master CPU and the slave CPU can be avoided, the data interaction time between cores is greatly shortened, and reliability, integrity and the like of data interaction can be guaranteed.

Description

technical field [0001] The present invention relates to the field of communication technology, and in particular to a data interaction method of a heterogeneous multi-core processor, a heterogeneous multi-core processor and a terminal. Background technique [0002] With the increasing application of heterogeneous multi-core processors in industrial scenarios, inter-core communication is the main difficulty faced by multi-core processor systems. The quality of the communication mechanism directly affects the performance of multi-core processors. Efficient communication The mechanism is an important guarantee for the high performance of multi-core processors. [0003] However, at present, most of the communication and data interaction between multi-core processors are based on the operating system, that is, both the master and the slave end run the operating system. Communication and data interaction methods between operating systems include widely used shared memory methods,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/167
Inventor 熊友军杨国平董浩赵明国
Owner UBTECH ROBOTICS CORP LTD
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