Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Robust design method for non-standard input vesa timing sequence

A design method and a robust technology, applied in the field of video processing, can solve problems such as abnormal output images, bad processing methods, and robustness of output images, and achieve the effects of solving logic processing problems, easy hardware logic implementation, and clear design structure

Active Publication Date: 2019-04-12
LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
View PDF5 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the process of image conversion and processing, because the input VESA timing sequence does not necessarily fully comply with the VESA standard timing sequence, the logic has a great impact on the robustness of the output screen by the way the input VESA protocol data is processed.
Bad processing methods may lead to abnormal output screen

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Robust design method for non-standard input vesa timing sequence
  • Robust design method for non-standard input vesa timing sequence
  • Robust design method for non-standard input vesa timing sequence

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] Embodiments of the present invention are described in detail below, and the embodiments are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0023] In the standard vesa timing, VS, HS, and DE have strict timing correspondence. However, in the actual circuit, the input VESA timing does not fully meet the VESA timing standard. The common non-standard input VESA timing has the following situations (take the resolution of 1280*1024@60Hz as an example):

[0024] 1. VS and HS do not change to high level at the same clock rising edge;

[0025] 2. One line is not equal to 1688 clock cycles (the number of effective pixels is 1280);

[0026] 3. The number of lines in the blanking period is not equal to 42 lines (the effective number of DE lines is 1024);

[0027] 4. DE high level time is not equal to 1280 clocks.

[0028] 5. The number of input lines is not equal to 1024 lines.

[0029] Due to the logic ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a robust design method for a non-standard input vesa timing sequence. The method comprises the following steps: firstly, carrying out row counting on a video effective signal DEin an input vesa timing sequence signal, judging whether a frame of data is complete or not, and then, using a synchronous processing mechanism to carry out clock synchronization processing on the video effective signal DE and a video data signal QE; and finally, taking each DE rising edge of the input vesa as a benchmark, adopting a three-section type state machine mechanism, and generating a standard DE effective timing sequence and relative standard HS and VS timing sequences according to a vesa standard timing sequence parameter. According to the method in the invention, the non-standardvesa timing sequence can be converted into a relative standard vesa timing sequence, and the data effective signal and the video data are ensured to meet the vesa timing sequence standard.

Description

technical field [0001] The invention relates to the technical field of video processing, in particular to the conversion of VESA timing, in particular to a robust design method for non-standard input VESA timing. Background technique [0002] At present, pre-distortion technology is generally used in civil aircraft head-up display and other digital head-up display to preprocess the input video image to eliminate the distortion of the optical system. However, in the process of image conversion and processing, since the input VESA timing sequence does not necessarily fully comply with the VESA standard timing sequence, the logic has a great impact on the robustness of the output image by the way the input VESA protocol data is processed. Bad processing methods may lead to abnormal output screen. It is necessary to propose a robust design method for non-standard input VESA timing, and correct the input non-standard timing to ensure the correctness of the VESA timing output to ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/04H04N5/06H04N5/14
CPCH04N5/04H04N5/06H04N5/14
Inventor 赵学娟苏霖王全忠
Owner LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products