A method for standard interface transmission of high-speed serial compute expansion bus

Abstract

The invention discloses a method for standard interface transmission of a high-speed serial compute expansion bus, which is used between two digital signal processing chips (DSP). The method including: step 1, establishing a transmission system;2, starting that power / clock of the high-speed serial compute bus standard (PCIE); 3, setting that root complex mode or the endpoint mode as the operationmode of the high-speed serial computer bus standard (PCIE) and configuring a serial / deserialization register (SERDE); Step 4, configuring the size of the base address memory (Base Address Register); 5, setting an exit or entry register; 6, establishing a transmission link connection. The invention overcomes the problem that the communication between two pieces of digital signal processing is transmitted to a field programmable gate array (FPGA) through one piece of digital signal processing, and the field programmable gate array (FPGA) transmits another piece of digital signal processing circuitous communication.

Description

technical field [0001] The invention relates to a transmission method between two digital signal processing chips (DSP), in particular to a high-speed serial computer bus standard (PCIE) interface transmission method used between two digital signal processing chips (DSP) . Background technique [0002] The high-speed serial computer bus standard (PCIE) has many obvious advantages, among which the characteristics of processor independence, bus master control, buffered isolation and true plug and play are the most important. The first-generation and second-generation input-output (IO) buses are all parallel data transmission buses. The bus includes multiple address lines, data lines, and control lines. Multiple peripheral devices can be connected to the bus. Because these peripheral devices are all connected to the same bus of the system, the data bandwidth of the bus is also shared by these peripheral devices. With the development of technology, the speed of devices connect...

AI Technical Summary

Problems solved by technology

However, considering the integrity requirements of the bus, when there are more external devices on the bus, the frequency will be lower, which restricts the clock frequency of the bus.

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