A multiplication device and method

A multiplication operation and operation device technology, which is applied in the field of computer operation processing, can solve problems such as complexity limitations, and achieve the effect of reducing complexity

Inactive Publication Date: 2019-01-29
北京探境科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At this stage, the complexity of the multiplier is directly related to the bit width of the multiplier. Sometimes limited by the complexity, a multiplier with a smaller bit width must be used to complete the multiplication of a larger bit-width multiplier

Method used

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  • A multiplication device and method
  • A multiplication device and method

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Embodiment Construction

[0037] The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0038] The multiplication operation device in the embodiment of the present invention realizes multiplication operations in three modes: the first multiplication mode 8X8 multiplication, marked as MODE_8x8; the second multiplication mode 16X8 multiplication, marked as MODE_16x8; the third multiplication mode 16X16 multiplication, marked as MODE_16x16. The number represents the bit width.

[0039] see figure 1 , specifically provide a multiplication operation device, the operation device includes:

[0040] The multiplier input module 1 is used to input the multipliers A and B of a given bit width to the multiplier of N×N;

[0041] The high and low bit splitting module 2 is used to split the high and low bits of the given bit width multipliers A and B;

[0042] The high and low bit marking module 3 is used to mark the high and low bit...

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PUM

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Abstract

The invention discloses a multiplication device and a multiplication method. A multiplier input module is called to input a multiplier with wide positioning to a multiplier. A high and low bits of thepositioning wide multiplier are split by calling the high and low bits splitting module. A complement module is called to complement the bit value after splitting; a multiplication module is called to perform multiplication operation on the bit value after complementing according to the given multiplication mode, and the operation result corresponding to the multiplication mode is obtained. A time-sharing transport module selects results obtained through multiplication according to a first multiplication mode, a second multiplication mode and a third multiplication mode in a time-share manneraccording to a given sequence and sends to an adder. A result accumulating module is called to accumulate the multiplication result sent to the adder to obtain the multiplier operation value. The invention realizes the support of the low bit width multiplier to the high bit width operation through the time expansion, solves the problem of completing the multiplication operation of the large bit width multiplier through the multiplier with less bit width, and reduces the complexity of the multiplication operation.

Description

technical field [0001] The invention relates to the technical field of computer operation processing, in particular to a multiplication operation device and method. Background technique [0002] Multiplication is one of the most common operations in information processing. The most basic operations that a computer can complete are: + (-) and shift left and right. Although there are generally multiplication instructions in the computer system hierarchy, the final meta-operations after decoding are addition and shift instructions. There are only 0 and 1 in the computer, so there is binary counting, such as 5=101, abstractly speaking, any number can be expressed in the form of 0 and 1. For a computer, shifting one bit to the left means multiplying by 2, and shifting one bit to the right means dividing by 2. Therefore, for multiplying a by x, just shift a to the left by the bit where x is 1 and accumulate. [0003] A multiplier is an electronic device that multiplies two unc...

Claims

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Application Information

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IPC IPC(8): G06F7/523
CPCG06F7/523
Inventor 鲁勇周韧研
Owner 北京探境科技有限公司
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