An automatic scoring method for an on-line Verilog code automatic judgment system

Abstract

The invention discloses an automatic scoring method of an on-line Verilog code automatic judgment system. The system accesses a standard answer database and copies the corresponding standard answer file and stores it in a temporary folder. The system runs the. Do file in the standard answer folder, and the. Vt file compiles the Verilog code file submitted by the students, and loads the library. The system runs modelsim in Linux to simulate. Vt, performs simulatin according to Verilog file submitted by students, and intercepts the console to output to. Result file; according to the time range written in the. Tm file, the system compares the simulation results. Result file with the standard answer. Cmp file to get the score result The. Do file of the invention compiles the student answer. Vfile and the. Vt file in the answer folder by using the vsim instruction, and simulates according to the. Vt file. The modules to be tested, the excitation of each signal, and the instructions to grabthe signal are written in the. Vt file. Thus, the whole Verilog code decision system is constructed, and the cost of Verilog class decision is greatly reduced.

Description

technical field [0001] The invention relates to online code automatic judgment in the field of online education, in particular to an automatic scoring method for an online Verilog code automatic judgment system. Background technique [0002] In the online education process of EDA (Electronic Design Automatic) course, judging Verilog questions is a brand-new online education method with a wide application prospect; the key to realize the function of judging Verilog questions is to design and Implement a set of algorithms for Verilog code parsing, simulation and judgment under existing EDA tools, especially for Verilog code parsing and simulation; in traditional technologies, it is usually a system for judging questions about c or c++ codes, which is applied to In the ACM competition, there is no system for judging Verilog code. Contents of the invention [0003] The embodiment of the present invention provides an automatic scoring method of an online Verilog code automatic...

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Problems solved by technology

[0002] In the online education process of EDA (Electronic Design Automatic) course, judging Verilog questions is a brand-new online education method with a wide application prospect; the key to realize the function of judging Verilog questions is to design and Realize a set of algorithms for Verilog code parsing, simulation and judgment under existing EDA tools, especially for Verilog code parsing and simulation; in traditional technologies, it is usually a system for judging questions about c or c++ codes, which is applied to In the ACM competition, there is no system for judging Verilog code

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