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Gate driving circuit, driving method thereof and display device

A gate drive circuit and drive group technology, applied to static indicators, static memory, instruments, etc., can solve problems such as display energy consumption

Active Publication Date: 2018-07-31
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the actual display process, when the resolution of the image to be displayed is lower than the intrinsic resolution of the display device, if the display device still displays at the intrinsic resolution, unnecessary display power consumption will be caused.

Method used

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  • Gate driving circuit, driving method thereof and display device
  • Gate driving circuit, driving method thereof and display device
  • Gate driving circuit, driving method thereof and display device

Examples

Experimental program
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Effect test

Embodiment 1

[0055] In this embodiment, the resolution that can be displayed by the display device with the above-mentioned gate driving circuit is an inherent resolution of 8K. In addition, the display device can also realize resolution conversion from 8K to 4K or conversion from 8K to 2K.

[0056] In this case, any one driving group 01 of the gate driving circuit is connected to 16 gate lines. Such as figure 2 Any one of the drive groups 01 shown above includes a first shift register unit 10_1 , a second shift register unit 10_2 , and a third shift register unit 10_3 cascaded in sequence.

[0057] Wherein, any shift register unit in the first shift register unit 10_1, the second shift register unit 10_2 and the third shift register unit 10_3 includes a first buffer subunit BF_1, a second buffer subunit BF_2, a third The buffer subunit BF_3 and the fourth buffer subunit BF_4.

[0058] In this case, the clock signal terminals CK of the first buffer subunit BF_1, the second buffer subuni...

Embodiment 2

[0075] In this embodiment, the display device having the above-mentioned gate driving circuit can realize the conversion of the resolution from the native resolution of 8K to 4K.

[0076] In this case, any one driving group 01 of the gate driving circuit is connected to 16 gate lines. Such as Figure 6 Any one of the drive groups 01 shown above includes a first shift register unit 10_1 , a second shift register unit 10_2 , a third shift register unit 10_3 and a fourth shift register unit 10_4 cascaded in sequence.

[0077] Wherein, any shift register unit in the first shift register unit 10_1, the second shift register unit 10_2, the third shift register unit 10_3 and the fourth shift register unit 10_4 includes the first buffer subunit BF_1, the second Two buffer subunits BF_2.

[0078] In this case, the clock signal terminals CK of the first buffer subunit BF_1 and the second buffer subunit BF_2 in the first shift register unit 10_1 are connected to the first system clock ...

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PUM

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Abstract

An embodiment of the present invention provides a gate driving circuit, a driving method thereof and a display device and relates to the technical field of the display, and the conversion of multiplepixel resolutions can be achieved. The gate driving circuit includes N cascaded shift register units. A driving group is formed by every S shift register units cascaded in turn. Each shift register unit includes a control subunit and at least two buffer subunits. The clock signal ends of any two buffer subunits in the same driving group are connected to different system clock signal ends. The clock signal ends of the control subunit and the buffer subunits in the same shift register unit are connected to different system clock signal ends.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a gate driving circuit, a driving method thereof, and a display device. Background technique [0002] A display device, for example, an LCD (Liquid Crystal Display, liquid crystal display device) includes an array substrate and a color filter substrate that are opposed to each other. Wherein, the array substrate includes a plurality of gate lines and a plurality of data lines intersecting horizontally and vertically, and each gate line intersects with a data line to define a sub-pixel. In this case, the inherent resolution of the display device is determined by the number and spacing of the gate lines and data lines. [0003] With the continuous development of high-definition technology, in order to meet the display requirements of high-definition images, the inherent resolution of display devices is getting higher and higher. However, in an actual display process, whe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36
CPCG09G3/3677G09G2310/0286G09G3/20G11C19/28G09G2310/0267G09G2310/0205G09G2340/0414G09G3/3266G09G2310/08G09G2330/023G09G2340/0407
Inventor 金志河韩承佑商广良郑皓亮姚星王志冲韩明夫袁丽君林允植吕敬董学
Owner BOE TECH GRP CO LTD
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