Method for optimizing efficient clock tree physical wiring in rear-end design of integrated circuit semi-customization

Abstract

The invention discloses a method for optimizing efficient clock tree physical wiring in rear-end design of integrated circuit semi-customization. The method comprises the following steps of:S1, obtaining wiring resource information by a rear-end design tool according to a chip shape and an internal component layout plan; S2, gradually checking and judging whether clock tree signals wire is reasonable or not according to the wiring resource information and sequences of check items with preset priorities, if the judging result is positive, returning to the step S1, and otherwise, executing stepS3; and S3, gradually optimizing the clock tree signal wires according to sequences of optimization items with preset priorities, outputting an optimization result, and executing the step S2 at the same time until all the check items are completed. According to the method for optimizing efficient clock tree physical wiring in rear-end design of integrated circuit semi-customization, the design quality of clock tree design is improved, benefit is brought to improve the working efficiency of chip design, the ineffective work and design iteration frequency are decreased, and the chip design period is finally shortened.

Description

technical field [0001] The invention belongs to the technical field of design automation EDA in the integrated circuit design industry, and in particular relates to an efficient clock tree physical winding optimization method for integrated circuit semi-customized back-end design. Background technique [0002] Clock tree design plays an important role in chip design. Whether the design of the clock tree is reasonable or not is directly related to whether the final performance of the integrated chip meets the design requirements. In the clock tree design, it is necessary to optimize the design several times according to the initial design quality. Among them, the physical routing optimization of the clock tree signal line is very important. [0003] At present, there is no uniform and efficient method for optimizing the physical routing of clock tree design in the industry. Correspondingly, conventional clock tree design physical design methods have problems such as poor d...

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Problems solved by technology

Correspondingly, the conventional clock tree design physical design method has problems such as poor design quality and long iteration time.

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