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Netlist simulation verification method and device

A technology of simulation verification and netlist, applied in design optimization/simulation, special data processing applications, instruments, etc., can solve problems such as project delay, slow netlist simulation process, loss of function development iterations, etc., to speed up and save manpower cost, work efficiency improvement effect

Inactive Publication Date: 2018-05-18
TIANJIN CHIP SEA INNOVATION TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the process of netlist simulation is slower, and some even take several weeks to complete the netlist simulation, resulting in project delays or losses caused by functional development iterations due to serious defects

Method used

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  • Netlist simulation verification method and device
  • Netlist simulation verification method and device
  • Netlist simulation verification method and device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0054] This embodiment provides a netlist simulation verification method, such as figure 1 with figure 2 As shown, the method includes the following steps:

[0055] Step S101, according to the verification environment of the sub-module to be tested, instantiate the netlist of the whole system.

[0056] When testing a sub-module split in the pre-simulation stage, the verification environment of the sub-module is used to instantiate the netlist of the whole system. For example, when using C language to design an integrated circuit verification program, the class model of the sub-module can be used to define the parameters of the netlist of the whole system.

[0057] Step S102, inputting a set clock excitation signal to the system-wide netlist, so that the system-wide netlist generates timing.

[0058] Before entering the netlist simulation stage, the clock tree is inserted into the system-wide netlist during the netlist synthesis process and place-and-route process. Clock s...

Embodiment 2

[0065] This embodiment provides a more preferred netlist simulation verification method, such as image 3 As shown, the method includes the following steps:

[0066] Step S301, according to the verification environment of the sub-module to be tested, instantiate the netlist of the whole system.

[0067] Step S302, inputting a set clock excitation signal to the system-wide netlist, so that the system-wide netlist generates timing.

[0068] Step S303, eliminating asynchronous paths that do not meet the timing.

[0069] Because the netlist verification tool will report an error for the path that does not meet the timing, and output an indeterminate state at the Q terminal of the D flip-flop. However, the asynchronous path does not meet the inspection of the setup time and hold time, so the asynchronous path needs to be eliminated. A specific method may be: generating all asynchronous paths in the netlist of the whole system through an asynchronous path search script; taking al...

Embodiment 3

[0077] This embodiment provides a netlist simulation verification device corresponding to the above method embodiment, such as Figure 4 As shown, the device includes:

[0078] The environment building module 41 is used for instantiating the netlist of the whole system according to the verification environment of the sub-module to be tested;

[0079] The clock excitation module 42 is used to input the set clock excitation signal to the netlist of the whole system, so that the netlist of the whole system can generate timing;

[0080] The simulation verification module 43 is used to adopt the existing test case to carry out the simulation verification of the sub-module to be tested in the netlist of the whole system;

[0081] The display module 44 is used for displaying the result of simulation verification.

[0082] Wherein, the environment establishment module 41 is also used to instantiate the netlist of the whole system using the verification environment of the sub-modules...

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Abstract

The invention provides a netlist simulation verification method and device, and belongs to the technical field of integrated circuit designing. According to the method and device, a system-wide netlist is instantiated according to a verification environment of a to-be-tested sub-module, simulation verification is conducted on the to-be-tested sub-module in the system-wide system netlist by adopting an existed test case, and therefore seamless connection between the pre-simulation and the post-simulation is achieved to accelerate the speed of netlist simulation verification; sub-module verification personnel do not need to re-familiar with a system-wide test environment and a system-wide function RTL, and positioning of a simulation problem can be carried out to prevent waste of time on a testing environment and RTL codes which are not related to test functions to improve working efficiency and save the labor cost.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a netlist simulation verification method and device. Background technique [0002] With the development of microelectronic design technology, digital integrated circuits have gradually developed from electron tubes, transistors, small and medium-scale integrated circuits, and ultra-large-scale integrated circuits to today's Application Specific Integrated Circuit (ASIC). Some products that people use in work and life, such as computers, mobile phones, digital TVs, etc., all use complex ASICs, and digital logic devices have also developed from simple logic gates to complex SOC (System On Chip, System-on-a-chip), providing flexible support for complex systems. [0003] With the continuous development of digital circuit systems, the logical complexity and scale of the system are increasing day by day, and the design methods of digital systems are also constantly e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/20
Inventor 钟丹徐庆阳刘冬培刘勤让朱珂宋克吕平沈剑良张丽丁青子黑建平杨晓龙田晓旭杨堃汪欣丁旭汤先拓
Owner TIANJIN CHIP SEA INNOVATION TECH CO LTD
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