Logic product yield monitoring structure and design method thereof

Abstract

The invention discloses a logic product yield monitoring structure and a design method thereof. The logic product yield monitoring structure comprises a monitoring storage unit and a peripheral circuit, wherein the monitoring storage unit is formed by combining every two inverters designed through a logic operation standard unit; and the monitoring storage unit is matched with the peripheral circuit through a circuit-level simulation program, so that logic product yield monitoring is realized. Through the logic product yield monitoring structure, the defect of a traditional SRAM test structurecan be overcome; and the structure is introduced at a development stage, so that a product-level yield problem is solved before a product yield is imported, the product mass production cycle is effectively shortened, and the purpose of quickly improving output is achieved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a logic product yield monitoring structure and a design method thereof. Background technique [0002] With the development of high-level processes, the technical difficulty increases exponentially. What is most needed in process development is the "eye" to monitor the process, that is, various test structures (Test key / Test vehicle) are needed to confirm the abnormal points of the process in the first time, so as to improve and shorten the process development cycle in time. [0003] At present, due to the limited technical accumulation of domestic preparation manufacturers and the serious shortage of human resources invested in process development, there is an extremely lack of development and application of a complete set of high-level process development and testing structures to achieve high-level process technology development. Continue to develop, avoid using do...

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Problems solved by technology

[0006] The present invention is aimed at the prior art, the traditional SRAM test structure cannot completely and effectively detect the health of the process, which easily leads to a high SRAM yield rate, but the product yield rate is far lower than the SRAM yield rate after the product is introduced, resulting in a very slow increase in the yield rate , and SRAM cannot detect defects such as product yield problems to provide a logical product yield monitoring structure

[0007] Another purpose of the present invention is to aim at the prior art, the traditional SRAM test structure can not fully effectively detect the health of the process, which easily leads to a high SRAM yield rate, but the product yield rate is far lower than the SRAM yield rate after the product is introduced, resulting in a high yield rate. The rate increase is very slow, and SRAM cannot detect defects such as product yield problems. Provide a design method for logic product yield monitoring structure

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