Wide range glitchless switchable clock divider with modified 2/3 divider stages

Abstract

A divider includes 2 / 3 divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A 2 / 3 divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled statein which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.

Description

technical field [0001] The present invention relates to a frequency divider, and more particularly to a frequency divider using 2 / 3 frequency division stages. Background technique [0002] Frequency dividers are used in many different applications. For example, frequency divider applications include programmable frequency dividers, multimode frequency dividers in fractional-N phase-locked loops, and integer frequency dividers in interpolating frequency dividers. [0003] Dividers range from simple divide-by-2 circuits to more complex dividers such as multimode dividers. Figures 1A-1C A basic divide-by-two frequency divider 100 is shown. Figure 1A A high-level representation of a divide-by-two divider is shown. The input signal (ck_in) 101 is divided by two and provided as output signal (ck_out) 103 . Figure 1B An implementation of frequency divider 100 is shown where output 103 is inverted and fed back to the input of flip-flop 105 . Figure 1C A state machine is show...

AI Technical Summary

Problems solved by technology

One way to increase the range of the divider is to force the downstream stage to output a valid mod_out signal, thus shortening the divider chain

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