Bus deadlock recovery system and method

Abstract

The invention relates to a bus deadlock recovery system and method. The recovery system comprises an I2C bus, main equipment and subsidiary equipment, the main equipment and the subsidiary equipment are connected to the I2C bus, the main equipment comprises an input output interface, a detection module and a control module, and the input output interface is grounded or connected with a clock lineof the I2C bus; the detection module is used for detecting the state of a clock signal transmitted on the I2C bus and the state of a data signal and judging whether the I2C bus is in a deadlock stateor not according to the detection result; the control module is connected with the input output interface and the detection module separately, and when the I2C bus is in a deadlock state, the controlmodule makes the clock signal become a low level signal after a preset duration by controlling the input output interface, so that the I2C bus is recovered from the deadlock state. On the condition that a recovery signal line or a buffering device is not added, deadlock of the I2C bus is removed, and the stability and the reliability of the I2C bus are improved.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a bus deadlock recovery system and method. Background technique [0002] The I2C bus is a two-wire serial bus widely used in embedded system devices to realize communication between the main controller and peripherals. The I2C bus includes a bidirectional data line (Serial Data, SDA) and a clock line (Serial ClockLine, SCL). Each I2C device connected to the I2C bus can be used as a master device to be responsible for the generation of bus clock, start signal and related initialization data, or as a slave device to be an addressed object. At least one master device and at least one slave device are connected to the I2C bus. [0003] In actual communication, the master device first sends a start signal to address the slave device on the I2C bus, and the slave device can perform corresponding read and write operations after responding. The length of the read and write data ...

AI Technical Summary

Problems solved by technology

The length of the read and write data is in bytes. Every time the slave device receives a byte, it sends an answer signal (AK). When disturbed, the clock signal remains high and the data signal remains low. I2C The bus enters a locked state and cannot be released

Generally, the method of adding a reset line or a buffer device for detecting the reset signal in the middle of the I2C bus is used to restore the I2C bus to normal, which increases the cost and complexity of the I2C system

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