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Parallel bus automatic compensation method based on FPGA

An automatic compensation and bus technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems such as signal asynchronous, unreliable data transmission, signal failure, etc., to ensure reliable sampling, solve signal asynchronous phenomena, and avoid bit errors high rate effect

Inactive Publication Date: 2017-10-24
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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AI Technical Summary

Problems solved by technology

However, due to the large number of signal lines and the non-uniform signal transmission delay of the parallel bus, the signal is not synchronized during bus sampling, and individual signal sampling failures are prone to occur. Especially when the bus frequency is high, it will cause bit errors and data The occurrence of problems such as unreliable transmission

Method used

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  • Parallel bus automatic compensation method based on FPGA
  • Parallel bus automatic compensation method based on FPGA

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Embodiment Construction

[0026] The present invention provides a kind of parallel bus automatic compensation method based on FPGA:

[0027] Among them, before the normal operation of the parallel bus, the processor is used to send a low-level signal on the parallel bus for FPGA sampling, and then a high-level signal is sent on the parallel bus for FPGA sampling;

[0028] The FPGA obtains the level change moment of all signal lines, and takes the level change moment of one signal line in the parallel bus as the reference time;

[0029] When the parallel bus is running normally, the FPGA performs clock compensation for the sampling time of other signal lines on the parallel bus according to the reference time.

[0030] At the same time, it provides an FPGA-based parallel bus automatic compensation system, including FPGA modules, processors,

[0031] Wherein, before the normal operation of the parallel bus, the processor is used to send a low-level signal on the parallel bus for the FPGA module to sampl...

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Abstract

The invention discloses a parallel bus automatic compensation method based on an FPGA, and relates to the technical field of embedded system communication. Before a parallel bus runs normally, a processor is used for sending out a low-level signal on the parallel bus to be sampled by the FPGA, and then a high-level signal is sent out on the parallel bus to be sampled by the FPGA; the FPGA acquires level change moments on all signal lines, and the level change moment on one signal line in the parallel bus serves as a reference moment; when the parallel bus runs normally, the FPGA conducts clock compensation on sampling time of other signal lines separately on the parallel bus according to the reference moment.

Description

technical field [0001] The invention discloses a bus automatic compensation method, relates to the technical field of embedded system communication, in particular to an FPGA-based parallel bus automatic compensation method. Background technique [0002] Bus Bus is a public communication trunk line for transmitting information between various functional components of the computer. It is a transmission harness composed of wires. According to the types of information transmitted by the computer, the bus of the computer can be divided into data bus, address bus and control bus. Used to transmit data, data address and control signals. However, due to the large number of signal lines and the non-uniform signal transmission delay of the parallel bus, the signal is not synchronized during bus sampling, and individual signal sampling failures are prone to occur. Especially when the bus frequency is high, it will cause bit errors and data Problems such as unreliable transmission occu...

Claims

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Application Information

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IPC IPC(8): G06F13/42
Inventor 曹刚秦刚朱书杉
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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