Cache management method and device and field programmable gate array

Abstract

The invention provides a cache management method and device and a field programmable gate array, and relates to the technical field of data caching. The cache management method and device and the field programmable gate array are used for increasing the bandwidth of a cache system. The method comprises the steps of cutting an enqueue message into at least one data slice according to the size of a preset slice and the length of the enqueue message when the enqueue message is received; allocating cache channel numbers to all the data slices; sending the data slices to data cache controllers of corresponding data cache channels according to the data cache channel numbers allocated to the data slices; writing the data slices into corresponding data cache under the control of the data cache controllers; receiving cache addresses and cache lengths returned by the data cache, and generating cache descriptors of all the data slices according to the data cache channel numbers allocated to the data slices and the cache addresses and the cache lengths returned by the data cache; writing the cache descriptors of all the data slices into BD cache. The cache management method and device and the field programmable gate array are used for cache management.

Description

technical field [0001] The invention relates to the technical field of data cache, in particular to a cache management method, device and field programmable gate array. Background technique [0002] With the development of information technology and network technology, caching technology has gradually become a popular and indispensable field. Caching technology refers to high-speed data exchange, so caching technology has greatly improved the response speed of the system. However, the storage capacity of traditional caching devices is usually limited, so that the stored content is also relatively limited, so caching management is a hot research issue in this field. [0003] refer to figure 1 As shown, the cache system in the prior art includes: a data packet input circuit 11 , a cache interface circuit 12 , a linked list management circuit 13 , a scheduling circuit 14 , a data output circuit 15 , a data cache 16 and a linked list memory 17 . figure 1 The cache management p...

AI Technical Summary

Problems solved by technology

[0004] Although the above cache management system can make the performance of any number of queues very close, the bandwidth provided by the above cache system is extremely limited

Specifically, when the 64bit bandwidth DDR4 works at a rate of 2400Mbps, the physical bandwidth is only 153Gbps, and the bandwidth utilization rate of the 64byte short packet of the 64bit wide DDR controller is very low, only about 20%. The two-way bandwidth is only 153*0.2=30.72Gbps, and the one-way bandwidth is only about 15Gbps

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