A level conversion circuit and method

Abstract

A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a level conversion circuit and method. Background technique [0002] The level conversion circuit is widely used in various interface circuits and input and output units to realize the logic conversion of the level, figure 1 It is a schematic diagram of the circuit structure for level conversion in integrated circuit design. It is often used to convert the logic level from the ground level GND to the positive power supply VDD to the logic level from the negative power supply VNEG to the positive power supply VDD. For example, 0~ The voltage of 2.5V is converted into the voltage of -2.5~2.5V. refer to figure 1 As shown, the level conversion circuit includes 16 Metal-Oxide Semiconductor Field Effect Transistors (MOS-FET, Metal-Oxide Semiconductor Field Effect Transistor), represented by M1~M16 respectively; wherein, M1~M4 are used to MOS tubes for level conversion; M...

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Problems solved by technology

[0004] However, during the switching process of the input level signal Sp, due to the simultaneous switching of the level signals, M1 and M3, M2 and M4, M5 and M7, M6 and M8 may all be turned on at the same time, so that the positive power supply VDD to the negative power supply VNEG A loop is generated between them, resulting in leakage; this will not only consume more dynamic current, but also cause more burrs on the edge of the output voltage signal, making it difficult to provide a high-quality control level for the subsequent circuit

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