System and method for remotely upgrading field-programmable gate array (FPGA)

Abstract

The invention provides a system and method for remotely upgrading a field-programmable gate array (FPGA). The system comprises the FPGA, a central processing unit (CPU), a complex programmable logic device (CPLD) and a flash memory, wherein the CPLD is electrically connected with the CPU, the FPGA and the flash memory through corresponding interfaces; the CPLD simulates the data read-write operation time sequence of the flash memory and writes a to-be-upgraded mirror image file into the flash memory; the CPLD simulates the data read-write operation time sequence of the flash memory to read the mirror image file stored in the flash memory and write the mirror image file into the CPLD; the CPLD simulates the passive loading configuration interface time sequence of the FPGA to transmit the mirror image file in the CPLD to the FPGA. By the system, the success rate of FPGA chip configuration is increased, configuration time is shortened, and the occupancy of CPU resources is reduced.

Description

Technical field [0001] The invention belongs to the field of communication technology, and specifically relates to a system and method for remotely upgrading a field programmable gate array. Background technique [0002] Many communication devices will use FPGA chips for high-speed interface design to implement functions such as related interface protocols and data forwarding. So how to remotely update the FPGA image file is particularly important for the entire device. [0003] At present, the remote update of the FPGA image file mainly adopts the passive loading mode of the CPU simulating the FPGA chip. Using this remote update method will not only take up too much CPU-related processes, but also cause the passive loading of the FPGA image file due to errors in the timing of the passive loading of the GPIO pins of the CPU. When using CPU to simulate the timing of passive loading interface, the clock frequency is relatively low. If the image file of the FPGA chip is large, the l...

AI Technical Summary

Problems solved by technology

Using this remote update method will not only occupy too many CPU-related processes, but also cause errors in the passive loading timing of the GPIO pins of the CPU, resulting in unsuccessful passive loading of the FPGA image file.

When the CPU is used to simulate the passive loading interface timing, the clock frequency is relatively low. If the image file of the FPGA chip is large, the loading process will be very slow.

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