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A scan chain test device and its implementation method

A technology for testing devices and implementation methods, which is applied in measuring devices, electronic circuit testing, measuring electronics, etc. It can solve problems such as no production test of circuits, security-sensitive data protection, and non-safe protection methods, and achieve extensive test coverage. and security coverage capability, correct test function, and increase the difficulty of cracking

Active Publication Date: 2019-06-04
DATANG MICROELECTRONICS TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In other existing technologies, the method of controlling the scan chain test mode does not protect the most secure and sensitive data in the scan chain, and the test mode can be skipped through FIB (Focused Ionbeam) and other methods When protected, the original state of the data is still exposed to the outside
At the same time, since most of the scan chain tests are performed in third-party factories, the scan chain test mode needs to be shared with third parties, so the protection mode of the scan chain test mode is still in an unsafe state
However, the method of security division inside the integrated circuit will lead to the fact that the circuits that are not divided into the scan chain are not subjected to functional analysis for production testing, and there are also circuits that enter the scan chain that are completely unprotected.

Method used

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  • A scan chain test device and its implementation method
  • A scan chain test device and its implementation method
  • A scan chain test device and its implementation method

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Embodiment Construction

[0047] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other arbitrarily if there is no conflict.

[0048] The steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than here.

[0049] The embodiment of the present invention provides a scan chain test device and implementation method. For the scan chain test in the design for test (DFT) of integrated circuits, the device can effectively improve the circuit safety performance and strengthen the difficulty of detecting the in...

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Abstract

The invention discloses a scan chain test device and a realizing method; the scan chain test device comprises a scan chain logic circuit, an input decryption module, and an output encrypting module; the input decryption module is used for decoding inputted encryption data, and inputting decoded data to the scan chain logic circuit; the output encrypting module is used for encoding and outputting the data outputted by the scan chain logic circuit. The device and method can decode / encode the input and output data of the scan chain test circuit, thus testing scan chain performance correct, and ensuring chip internal data safety. In addition, the method and device can fully add all internal data of the integrated circuit into safety protection, thus providing wider test coverage ability and safety coverage ability.

Description

Technical field [0001] The invention relates to the field of integrated circuit design for test (DFT), in particular to a scan chain test device and an implementation method. Background technique [0002] As the scale of integrated circuit design becomes larger and smaller, the size of the process becomes smaller and smaller, and the ever-increasing integration level also increases the cost and difficulty of production test. Scan chain test method is an important design for test (DFT) Means, widely used to improve chip quality and yield. According to the scan chain test principle, the correctness test of the internal circuit can be completed, but it also brings security risks. Since the scan chain circuit connects all the registers in the integrated circuit in series, through the shift method, the scan chain input can send any value to any register of the circuit, and the input data is the response after the internal circuit completes the test logic function Data can be externa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2851
Inventor 刘小雷赵红敏
Owner DATANG MICROELECTRONICS TECH CO LTD
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