A memory data migration method and node controller

Abstract

Embodiments of the invention disclose a memory data migration method and a node controller (NC), and relate to the technical field of communications. The cross-QPI (Quick Path Interconnect) domain memory data migration can be realized. According to the specific scheme, the NC sends a first instruction message to a first CPU (Central Processing Unit), wherein the first indication message is used for instructing the first CPU to read memory data in a first address; the NC receives first data sent by the first CPU, wherein the first data is the memory data in the first address; the NC sends a second instruction message to the first CPU, wherein the second instruction message is used for instructing the first CPU to write the first data back to the first address; the NC determines a second address corresponding to the first address according to a pre-established mirror image relationship; and the NC sends a third instruction message to a second CPU, wherein the third instruction message is used for instructing the second CPU to write the first data back to the second address.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a memory data migration method and a node controller (English: Node Controller, abbreviation: NC). Background technique [0002] The migration of memory data refers to copying the memory data to be migrated from the memory where it is located (hereinafter referred to as the main memory) to the standby memory. When the copy is complete, the primary memory is replaced with the secondary memory, and subsequent access requests sent to the primary memory are sent to the secondary memory. [0003] At present, the high-speed interconnection between central processing units (English: Central Processing Unit, abbreviated: CPU) can be realized by adopting the Quick Path Interconnect (English: Quick Path Interconnect, abbreviated: QPI) technology, and the memory controller is integrated in the CPU, so that The CPU can directly access memory. Using QPI technology, interconne...

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Problems solved by technology

[0004] However, the above method has the following problems: a QPI domain can only include 8 CPUs at most, and if more CPUs are to be interconnected, an NC needs to be introduced, and the NC can be connected to different QPI domains, see image 3

To realize the migration of memory data across QPI domains, for example, the memory connected to CPU0 ( image 3 The memory connected to each CPU is not shown in the figure), and the memory data in the memory connected to CPU8 is migrated to the memory connected to CPU8, then CPU0 needs to send a write request to CPU8 through NC. However, since the CPUs send messages through a private protocol, NC cannot Identify which CPU the write request is sent to, so that the migration of memory data across QPI domains cannot be realized

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