Circuit system security protection chip

Abstract

The invention discloses a circuit system security protection chip. The chip comprises interface input and output logic, a dual-port RAM, internal data input and output logic, an encryption algorithm module, an interface control module, an internal register bank, a voltage detection module, a frequency detection module, a chip tamper-proofing module, a bus encryption module and a hardware 3DES algorithm coprocessor, wherein the control module is in bidirectional connection with the internal data input and output logic, the encryption algorithm module, the internal register bank and a DMA controller, and signals flow in two directions; the signal input end of the control module is connected with the signal output end of the interface input and output logic; the voltage detection module is used for resisting attacks by high and low voltages; the frequency detection module is used for resisting attacks by high and low frequencies; the chip tamper-proofing module is used for designing a unique serial number of the chip; the bus encryption module is provided with a metallic shield protective layer and used for self-destruction of internal data after external attacks are detected. Operation of the encryption chip and input of external data can be basically performed at the same time, and high speed of data flow read-write in a DMA burst read-write mode can be fully utilized to increase the data encryption and decryption speed of the chip.

Description

technical field [0001] The invention relates to computer chip technology, in particular to the design of a chip for circuit system safety protection. Background technique [0002] Two commonly used methods are widely used in the design of chips with block encryption algorithms. One is to adopt the traditional interface design method, that is, to exchange data with the CPU through an 8-32-bit data bus (VMS113data sheetrevision 2.1, 1999.5 .2, VLSI Technology Company) (PCC101product specification, Version 1.1, 2000.5.20, Pijnenburg CustomChips), if you want to improve the processing speed of the data stream, you must use the PIPELINE method. Because the read and write command cycle of a CPU always takes several clock cycles, this makes it difficult to complete the operation of reading and writing a set of data within the clock cycle specified when the block encryption algorithm chip works in PIPELINE mode , so that the application system cannot reach the highest speed of the ...

AI Technical Summary

Problems solved by technology

Because the read and write command cycle of a CPU always takes several clock cycles, this makes it difficult to complete the operation of reading and writing a set of data within the clock cycle specified when the block encryption algorithm chip works in PIPELINE mode , so that the application system cannot reach the highest speed of the chip design, even if the design can meet the requirements of the chip, it will occupy all the resources of the CPU

Another interface method is to combine the block encryption algorithm with the PCI bus controller (7751Encryption Processor data sheet, Hi / fn, Inc), so that the encryption and decryption data in the system with the PCI bus can be directly processed with the encryption algorithm part of the data Exchange, thereby improving the speed of data processing, but this approach will inevitably greatly reduce the design flexibility of the application system, and the cost of the chip will also increase a lot

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