Method for carrying out sub-module comprehensive design on circuit on basis of computer software

Abstract

The invention relates to a method for carrying out sub-module comprehensive design on a circuit on the basis of computer software. Modularized decomposition is carried out on the circuit; modules are divided according to the relationship between functions or subjects and peripherals; the method is determined according to different demands; module code compilation is carried out; analysis and troubleshooting are directly carried out on the modules with problems without checking the whole circuit; in the initial period of design, a sub-module assembly line manner is utilized so that the layout and wiring design of each module can be completed rapidly and efficiently; in the later period of the design, when the original code design needs to be modified as time series check or post-simulation has problems, the modification is narrowed to a corresponding sub-module, so that workloads of the re-synthesis, time series check and layout and wiring are decreased, the research and development period of each singe module is shortened, the research process of the whole circuit is accelerated and the efficiency is improved.

Description

technical field [0001] The invention relates to the field of electronic circuits, in particular to the field of computer-based electronic circuit design, and specifically refers to a method for comprehensively designing circuits by modules based on computer software systems. Background technique [0002] In the original touch control circuit, a top-down comprehensive structure is adopted, and all modules such as the main control, timer, and filter are placed together for layout and wiring. The disadvantage of this method is obvious, that is, all modules are placed together for cross-wiring. The design cycle is extended, timing violations occur, and the inspection path is complicated. On the whole, it causes problems such as long development cycle and difficult errors. [0003] The patent application number CN201310081242.3 discloses a module-level circuit netlist simulation method, including the RTL simulation process and the netlist simulation process; wherein, the delay in...

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Problems solved by technology

[0005] Therefore, how to further solve the problem of using a top-down synthesis structure in the prior art, placing all modules such as the main control, timer, and filter together for layout and wiring, prolonging the design cycle, timing violations, and complicated inspection paths On the whole, it has caused problems such as long R&D cycle and difficulty in making mistakes.

How to improve this method has become a major technical problem in the current field, and the existing technology cannot fundamentally overcome this problem

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