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High-resolution clock phase-shift architecture and algorithm implementation method

A high-resolution, clock-phase technology, applied in the direction of automatic power control, electrical components, etc., can solve problems such as low phase shift resolution

Inactive Publication Date: 2016-11-16
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although DCM and PLL provide some phase-shifted versions of the clock, they are all fixed degrees and the resolution of the phase shift is low. When using it, users cannot intuitively use degrees as the unit to move the phase by any degree.

Method used

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  • High-resolution clock phase-shift architecture and algorithm implementation method
  • High-resolution clock phase-shift architecture and algorithm implementation method
  • High-resolution clock phase-shift architecture and algorithm implementation method

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Embodiment Construction

[0036] The embodiments listed in the present invention are only used to help understand the present invention, and should not be interpreted as limiting the protection scope of the present invention. For those of ordinary skill in the art, they can also Improvements and modifications are made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0037] Such as figure 1As shown, CLKIN is the input clock. In order to make the reference phase-shifted clock highly match the target phase-shifted clock and offset the inherent phase delay, CLKIN enters DELAY_LINE0 and DELAY_LINE1 at the same time. CLKIN generates CLKOUT0 through DELAY_LINE0, CLK_PS_MUX0 and FINE_DELAY0, where CLK_PS_MUX0 is configured as a fixed 0, and FINE_DELAY0 is also configured as 0, that is, CLKOUT0 is the reference phase shift clock. CLKIN generates CLKOUT1 through DELAY_LINE1, CLK_PS_MUX1 and FINE_DELAY1, and CLKOUT1...

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Abstract

The present invention relates to a high-resolution clock phase shift architecture, including: coarse-grained clock phase delay chain DELAY_LINE1, clock phase selector CLK_PS_MUX1, fine-grained clock phase delay chain FINE_DELAY1, coarse-grained clock phase detector GENERAL_PD, fine-grained clock phase Phase detector FINE_PD, coarse-grained clock phase delay chain controller GENERAL_CTRL and fine-grained clock phase delay chain controller FINE_CTRL; at the same time, the present invention proposes a new algorithm, and obtains the input clock by twice phase discrimination and counter difference. Period, and then divide the input clock period into 360 equal parts to obtain the value of the counter corresponding to every 1 degree. The user can realize the phase shift of the clock by any degree by configuring the data of the corresponding degree to GENERAL_CTRL and FINE_CTRL.

Description

technical field [0001] The invention relates to the technical field of clock management, in particular to a high-resolution clock phase-shift architecture and an algorithm implementation method, which is used for phase shifting a clock by any degree. Background technique [0002] The digital clock management (DCM) in Field Programmable Gate Array (FPGA, Field Programmable Gate Array) mainly provides four functions: clock deskewing, frequency synthesis, phase shifting and dynamic reconfiguration. [0003] Phase shift is to move the phase of the clock according to the system settings or user requirements. Since the frequency of the input clock is different, that is, the period of the input clock is different, the unit of the phase shift is generally degrees. In many cases, a phase shift is required between the clocks. In FPGA, DCM can provide 180° and 90° phase shift, for example: CLK2X180, CLKFX180 are 180° phase shift versions of CLK2X and CLKFX respectively, CLK90, CLK180,...

Claims

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Application Information

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IPC IPC(8): H03L7/081H03L7/085H03L7/18
CPCH03L7/0814H03L7/085H03L7/18
Inventor 涂波单悦尔于宗光胡凯
Owner 58TH RES INST OF CETC
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